MT16LSDT6464AG-133D2 Micron Technology Inc, MT16LSDT6464AG-133D2 Datasheet - Page 9
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MT16LSDT6464AG-133D2
Manufacturer Part Number
MT16LSDT6464AG-133D2
Description
MODULE SDRAM 512MB 168DIMM
Manufacturer
Micron Technology Inc
Specifications of MT16LSDT6464AG-133D2
Memory Type
SDRAM
Memory Size
512MB
Speed
133MHz
Package / Case
168-DIMM
Main Category
DRAM Module
Sub-category
SDRAM
Module Type
168UDIMM
Device Core Size
64b
Organization
64Mx64
Total Density
512MByte
Chip Density
256Mb
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Current
1.096A
Number Of Elements
16
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
168
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use.
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
Burst Length
ented, with the burst length being programmable, as
shown in Mode Register Definition Diagram. The burst
length determines the maximum number of column
locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, or 8 loca-
tions are available for both the sequential and the
interleaved burst types, and a full-page burst is avail-
able for the sequential type. The full-page burst is used
in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in the Burst
Definition Table. The block is uniquely selected by A1–
A9 when the burst length is set to two; by A2–A9 when
the burst length is set to four; and by A3–A9 when the
burst length is set to eight. The remaining (least signif-
icant) address bit(s) is (are) used to select the starting
location within the block. Full-page bursts wrap within
the page if the boundary is reached, as shown in the
Table 7.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
09005aef80bccbe7
SD8_16C16_32x64AG.fm - Rev. E 12/05 EN
Mode register bits M0–M2 specify the burst length,
The mode register must be loaded when all device
Read and write accesses to the SDRAM are burst ori-
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
9
128MB (x64, SR), 256MB (x64, DR)
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 7.
to ensure compatibility
with future devices.
M11, M10 = “0, 0”
*Should program
The ordering of accesses within a burst is deter-
Figure 5: Mode Register Definition
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Reserved* WB
11
A11
10
A10
M9
0
1
168-PIN SDRAM UDIMM
9
A9
Op Mode
8
A8
7
A7
Programmed Burst Length
M8
Diagram
0
Single Location Access
-
CAS Latency
6
Write Burst Mode
A6
5
M7
©2003, 2004 Micron Technology, Inc. All rights reserved.
A5
0
-
4
A4
M3
BT
M6-M0
Defined
0
1
3
A3
-
M2
M6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
2
M1
M5
A2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
0
A0
Reserved
Reserved
Reserved
Full Page
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8