MT18VDDF6472DG-40BG2 Micron Technology Inc, MT18VDDF6472DG-40BG2 Datasheet - Page 11
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MT18VDDF6472DG-40BG2
Manufacturer Part Number
MT18VDDF6472DG-40BG2
Description
MODULE SDRAM DDR 512MB 184DIMM
Manufacturer
Micron Technology Inc
Specifications of MT18VDDF6472DG-40BG2
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
400MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184RDIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
256Mb
Access Time (max)
500ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.836A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 6:
NOTE:
Table 7:
pdf: 09005aef8074e85b, source: 09005aef8072fe49
DDF18C64_128x72G.fm - Rev. C 11/04 EN
LENGTH
1. For a burst length of two, A1
2. For a burst length of four, A2
3. For a burst length of eight, A3
4. Whenever a boundary of the block is reached within a
5. i = 9, 11 (512MB)
BURST
element block; A0 selects the first access within the
block.
element block; A0
block.
element block; A0
block.
given sequence above, the following access wraps
within the block.
i = 9, 11, 12 (1GB)
2
4
8
SPEED
-26A
-335
-262
-265
-202
A2 A1 A0
0
0
0
0
1
1
1
1
STARTING
ADDRESS
COLUMN
Burst Definition Table
CAS Latency (CL) Table
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
A0
–
–
75
75
75
75
75
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1 select the first access within the
A2 select the first access within the
CLOCK FREQUENCY (MHz)
CL = 2
ALLOWABLE OPERATING
ORDER OF ACCESSES WITHIN
f
f
f
f
f
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
SEQUENTIAL
133
133
133
100
100
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
–
–
–
Ai select the two-data-
Ai select the four-data-
Ai select the eight-data-
A BURST
75
75
75
75
INTERLEAVED
CL = 2.5
N/A
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
f
f
f
f
0-1
1-0
166
133
133
133
11
Read Latency
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 7, CAS
Latency Diagram.
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. The CAS
Latency Table indicates the operating frequencies at
which each CAS latency setting can be used.
known operation or incompatibility with future ver-
sions may result.
Operating Mode
MODE REGISTER SET command with bits A7–A12
each set to zero, and bits A0–A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
COMMAND
COMMAND
The READ latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
Reserved states should not be used, because un-
The normal operating mode is selected by issuing a
DQS
DQS
CK#
CK#
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 7: CAS Latency Diagram
CK
CK
184-PIN DDR SDRAM RDIMM
512MB, 1GB (x72, ECC, SR)
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
T1
T1
©2004 Micron Technology, Inc. All rights reserved.
T2
NOP
NOP
T2
T2n
T2n
DON’T CARE
T3
NOP
NOP
T3
T3n
T3n