MT18VDDF6472DG-40BG2 Micron Technology Inc, MT18VDDF6472DG-40BG2 Datasheet - Page 22
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MT18VDDF6472DG-40BG2
Manufacturer Part Number
MT18VDDF6472DG-40BG2
Description
MODULE SDRAM DDR 512MB 184DIMM
Manufacturer
Micron Technology Inc
Specifications of MT18VDDF6472DG-40BG2
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
400MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184RDIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
256Mb
Access Time (max)
500ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.836A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
pdf: 09005aef8074e85b, source: 09005aef8072fe49
DDF18C64_128x72G.fm - Rev. C 11/04 EN
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
once every 70.3µs; burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.
other specifications:
(
in direct porportion to the clock duty cycle and a
practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation
of 45/55, beyond which functionality is uncertain.
Figure 9, Derating Data Valid Window (
t
and 45/55.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
the input must:
DQSQ), shows duty cycles ranging between 50/50
a. Sustain a constant slew rate from the current
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
t
QH =
AC level through to the target AC level, V
or V
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
t
IH
HP -
(AC).
50/50
3.750
2.500
3.400
t
QHS). The data valid window derates
N/A
N/A
49.5/50.5
3.700
-26A/-265 @
-202 @
-26A/-265 @
-202 @
-335 @
t
3.350
2.463
HP (
t
t
t
CK = 10ns
CK = 8ns
CK = 6ns
t
Figure 9: Derating Data Valid Window
CK/2),
3.650
49/51
t
t
CK = 10ns
CK = 7.5ns
2.425
3.300
t
RFC [MIN]) else
t
DQSQ, and
48.5/52.5
3.600
2.388
3.250
IL
t
QH -
(AC)
(
48/52
t
3.550
t
QH
QH -
2.350
3.200
Clock Duty Cycle
22
t
DQSQ)
47.5/53.5
3.500
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
30.
31. READs and WRITEs with auto precharge are not
2.313
3.150
be 1V/ns (2V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4V/ns, functionality is uncer-
tain. For -335, slew rates must be
335, slew rates must be 0.5 V/ns.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
t
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
allowed to be issued until
fied prior to the internal precharge command
being issued.
DH for each 100mv/ns reduction in slew rate. If
HP min is the lesser of
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
184-PIN DDR SDRAM RDIMM
maintain at least the target DC level, V
or V
3.450
47/53
must not vary more than 4 percent if CKE is
512MB, 1GB (x72, ECC, SR)
2.275
3.100
IH
(DC).
46.5/54.5
3.400
2.238
3.050
3.350
46/54
2.200
3.000
©2004 Micron Technology, Inc. All rights reserved.
t
t
RAS (MIN) can be satis-
CL minimum and
45.5/55.5
3.300
2.163
2.950
0.5 V/ns. For -
3.250
45/55
2.125
2.900
t
DS and
IL
(DC)
t
CH