MT18VDDF6472DG-40BG2 Micron Technology Inc, MT18VDDF6472DG-40BG2 Datasheet - Page 29
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MT18VDDF6472DG-40BG2
Manufacturer Part Number
MT18VDDF6472DG-40BG2
Description
MODULE SDRAM DDR 512MB 184DIMM
Manufacturer
Micron Technology Inc
Specifications of MT18VDDF6472DG-40BG2
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
400MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184RDIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
256Mb
Access Time (max)
500ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.836A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
SPD Clock and Data Conventions
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 14, Data Validity, and Figure 15, Defi-
nition of Start and Stop).
SPD Start Condition
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
SPD Stop Condition
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
pdf: 09005aef8074e85b, source: 09005aef8072fe49
DDF18C64_128x72G.fm - Rev. C 11/04 EN
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
SDA
SCL
Data states on the SDA line can change only during
All commands are preceded by the start condition,
All communications are terminated by a stop condi-
Figure 14: Data Validity
DATA STABLE
Figure 16: Acknowledge Response From Receiver
DATA
CHANGE
DATA STABLE
29
SPD Acknowledge
cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Fig-
ure 16, Acknowledge Response From Receiver).
acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.
Figure 15: Definition of Start and Stop
SDA
SCL
Acknowledge is a software convention used to indi-
The SPD device will always respond with an
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
START
BIT
512MB, 1GB (x72, ECC, SR)
8
©2004 Micron Technology, Inc. All rights reserved.
Acknowledge
9
STOP
BIT