MT18VDDT6472AG-335G4 Micron Technology Inc, MT18VDDT6472AG-335G4 Datasheet - Page 20

• Manufacturer Part Number: MT18VDDT6472AG-335G4
• Description: MODULE SDRAM DDR 512MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDT6472AG-335G4

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 256Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.611A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC
Notes: 1–5, 12–15, 29; notes appear on pages 22–25; 0°C
pdf: 09005aef808a331f, source: 09005aef80858037
DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Operating Conditions
CL = 2.5
CL = 2
512MB, 1GB
256MB,
256MB, 512MB, 1GB, 2GB (x72, ECC, SR)
T
A
20
SYMBOL
t
t
t
+70°C; V
CK (2.5)
t
t
DQSCK
t
t
t
WPRES
t
t
t
t
t
CK (2)
DQSQ
t
DQSH
t
WPRE
WPST
DIPW
DQSL
DQSS
t
t
t
t
t
t
t
MRD
t
RPRE
t
RPST
t
QHS
t
t
t
DSH
t
t
t
t
IPW
RAS
RAP
t
RCD
RRD
t
DSS
t
t
RFC
t
t
QH
AC
CH
DH
IH
IH
DS
HP
HZ
RC
CL
LZ
IS
IS
RP
F
S
F
S
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
DD
7.5/10
-0.75
-0.75
-0.75
t
MIN
t
0.45
0.45
1.75
0.35
0.35
0.75
0.90
0.90
0.25
HP -
QHS
= V
7.5
0.5
0.5
0.2
0.2
2.2
0.9
0.4
0.4
15
40
20
65
75
20
20
15
1
1
0
-26A/-265
t
DD
CH,
Q = +2.5V ±0.2V
120,000
t
MAX
+0.75
+0.75
+0.75
CL
0.55
1.25
0.55
0.75
0.5
1.1
0.6
0.6
13
13
t
t
MIN
0.45
0.45
0.35
0.35
0.75
0.25
-0.8
-0.8
-0.8
QHS
HP -
0.6
0.6
0.2
0.2
1.1
1.1
1.1
1.1
2.2
0.9
0.4
0.4
10
16
40
20
70
80
20
20
15
8
2
0
t
CH,
©2004 Micron Technology, Inc. All rights reserved.
-202
120,000
t
MAX
+0.8
0.55
0.55
+0.8
1.25
CL
+0.8
0.6
1.1
0.6
0.6
13
13
1
UNITS
t
t
t
t
t
t
t
t
t
t
t
ns
CK
CK
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
ns
CK
NOTES
40, 46
40, 46
22, 23
16, 37
16, 37
22, 23
18, 19
26
26
23
23
30
12
12
12
12
31
44
38
38
17