MT18VDDT6472AG-335G4 Micron Technology Inc, MT18VDDT6472AG-335G4 Datasheet - Page 23

• Manufacturer Part Number: MT18VDDT6472AG-335G4
• Description: MODULE SDRAM DDR 512MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDT6472AG-335G4

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 256Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.611A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pdf: 09005aef808a331f, source: 09005aef80858037
DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN
22. The valid data window is derived by achieving
23. Each device has a corresponding DQS.
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
burst refreshing or posting by the DRAM control-
ler greater than eight refresh cycles is not allowed.
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyond which functionality is
uncertain. Figure 8, Derating Data Valid Window,
shows derating curves for duty cycles ranging
between 50/50 and 45/55.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
the input must:
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
a. Sustain a constant slew rate from the current
t
QH =
AC level through to the target AC level, V
or V
50/50
t
IH
HP -
3.750
2.500
3.400
(AC).
t
N/A
QHS). The data valid window derates
49.5/50.5
3.700
-26A/-265 @
-202 @
-26A/-265 @
-202 @
3.350
2.463
t
HP (
t
t
CK = 10ns
CK = 8ns
t
3.650
49/51
Figure 8: Derating Data Valid Window
t
t
CK/2),
CK = 10ns
CK = 7.5ns
2.425
3.300
t
RFC [MIN]) else
t
DQSQ, and
48.5/52.5
3.600
2.388
3.250
IL
256MB, 512MB, 1GB, 2GB (x72, ECC, SR)
48/52
3.550
(AC)
t
(
QH
t
2.350
3.200
QH -
Clock Duty Cycle
23
t
DQSQ)
47.5/53.5
3.500
26. CK and CK# input slew rate must be
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
30.
2.313
3.150
ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4V/ns, functionality is uncertain.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
t
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
DH for each 100mv/ns reduction in slew rate. If
HP min is the lesser of
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
184-PIN DDR SDRAM RDIMM
maintain at least the target DC level, V
or V
3.450
47/53
must not vary more than 4 percent if CKE is
2.275
3.100
IH
(DC).
46.5/54.5
3.400
2.238
3.050
3.350
46/54
©2004 Micron Technology, Inc. All rights reserved.
2.200
3.000
t
CL minimum and
45.5/55.5
3.300
2.163
2.950
1V/ns (2V/
t
3.250
45/55
DS and
IL
2.900
2.125
(DC)
t
CH