MT4VDDT864AG-265B1 Micron Technology Inc, MT4VDDT864AG-265B1 Datasheet
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MT4VDDT864AG-265B1
Specifications of MT4VDDT864AG-265B1
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MT4VDDT864AG-265B1 Summary of contents
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... DDR SDRAM UDIMM MT4VDDT864A – 64MB MT4VDDT1664A – 128MB MT4VDDT3264A – 256MB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 184-Pin DIMM (MO–206) OPTIONS • Operating Temperature Range Commercial (0°C to +70°C) Industrial (-40°C to +85°C) • ...
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Table 2: Part Numbers and Timing Parameters MODULE PART NUMBER DENSITY MT4VDDT864A(I)G-335__ MT4VDDT864A(I)Y-335__ MT4VDDT864A(I)G-262__ MT4VDDT864A(I)Y-262__ MT4VDDT864A(I)G-26A__ MT4VDDT864A(I)Y-26A__ MT4VDDT864A(I)G-265__ MT4VDDT864A(I)Y-265__ 128MB MT4VDDT1664A(I)G-335__ MT4VDDT1664A(I)Y-335__ 128MB 128MB MT4VDDT1664A(I)G-262__ MT4VDDT1664A(I)Y-262__ 128MB MT4VDDT1664A(I)G-26A__ 128MB MT4VDDT1664A(I)Y-26A__ 128MB MT4VDDT1664A(I)G-265__ 128MB MT4VDDT1664A(I)Y-265__ 128MB MT4VDDT3264A(I)G-335__ 256MB MT4VDDT3264A(I)Y-335__ 256MB MT4VDDT3264A(I)G-262__ ...
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Table 3: Pin Assignment (184-Pin DIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL DQ17 47 REF 2 DQ0 25 DQS2 DQ1 DQS0 ...
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DIMM Pinouts Front View U1 PIN 1 Back View PIN 184 Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS 63, 65, 154 16, ...
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... No Connect: These pins should be left unconnected. DNU – Do Not Use: These pins are not connected on this module but are assigned pins on other modules in this product family. 5 184-PIN DDR SDRAM UDIMM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Unless otherwise noted, resistor values are 22Ω wiring may differ from that described in this drawing; however DQ/ DM/ DQS relationships are maintained as shown. 3. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part numbering guide at www.micron.com/numberguide. pdf: 09005aef8085081a, source: 09005aef806e129d DD4C8_16_32x64AG ...
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... DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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... A11 A10 Operating Mode CAS Latency BT * M13 and M12 (BA1 and BA0) must be “0, 0” to select the base mode register (vs. the extended mode register). 128MB, 256MB Modules BA1 BA0 A12 A11 A10 Operating Mode CAS Latency BT * M14 and M13 (BA1 and BA0) must be “ ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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... DD4C8_16_32x64AG.fm - Rev. B 9/04 EN 64MB, 128MB, 256MB (x64, SR) 184-PIN DDR SDRAM UDIMM Figure 5: Extended Mode Register Definition Diagram 64MB Module BA1 BA0 A11 A10 Operating Mode 128MB, 256MB Modules BA1 BA0 A10 A12 A11 Operating Mode 2 E11 E10 E9 ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 64MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 18–21; 0°C ≤ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); CK ...
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Table 13: I Specifications and Conditions – 128MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 18–21; 0°C ≤ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); CK ...
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Table 14: I Specifications and Conditions – 256MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 18–21; 0°C ≤ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); CK ...
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Table 15: Capacitance Note: 11; notes appear on pages 18–21 PARAMETER Input/Output Capacitance: DQ, DQS/DM Input Capacitance: Command and Address: S#, CKE Input Capacitance: CK0, CK0# Input Capacitance: CK1, CK1#; CK2, CK2# Table 16: DDR SDRAM Component Electrical Characteristics and ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 13-15, 29, 48; notes appear on pages 18–21; 0°C to +70° CHARACTERISTICS PARAMETER LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 ...
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Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mV or 2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not ...
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Figure 9: Reduced Drive Pull-Down Characteristics 0.0 0.5 1.0 V (V) OUT f )The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10 percent, ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 12, Data Validity, and Figure ...
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Table 17: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 18: EEPROM Operating Modes MODE Current Address Read Random Address Read Sequential Read Byte ...
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Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to Vss; V DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs I = 3mA OUTPUT LOW VOLTAGE: OUT INPUT ...
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Table 21: Serial Presence- Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 27 BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory ...
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... The value of RP, RCD and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef8085081a, source: 09005aef806e129d DD4C8_16_32x64AG.fm - Rev. B 9/04 EN 64MB, 128MB, 256MB (x64, SR) 184-PIN DDR SDRAM UDIMM ENTRY (VERSION) ...
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Figure 16: 184-Pin DIMM Dimensions 0.079 (2.00 (4X) 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.091 (2.30) 0.050 (1.27) TYP. TYP. PIN 184 1.95 (49.53) TYP. NOTE: All dimensions are in inches (millimeters); Data Sheet Designation ...