MT4VDDT864AG-26AB1 Micron Technology Inc, MT4VDDT864AG-26AB1 Datasheet - Page 25
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MT4VDDT864AG-26AB1
Manufacturer Part Number
MT4VDDT864AG-26AB1
Description
MODULE SDRAM DDR 64MB 184DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT4VDDT864AG-265B1.pdf
(28 pages)
Specifications of MT4VDDT864AG-26AB1
Memory Type
DDR SDRAM
Memory Size
64MB
Speed
266MT/s
Package / Case
184-DIMM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 19: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to Vss; V
Table 20: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
NOTE:
pdf: 09005aef8085081a, source: 09005aef806e129d
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE:
INPUT LEAKAGE CURRENT: V
OUTPUT LEAKAGE CURRENT: V
STANDBY CURRENT: SCL = SDA = V
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
edge of SDA.
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
I
PARAMETER/CONDITION
OUT
= 3mA
SS
IN
; V
OUT
= GND to V
DDSPD
DDSPD
DD
= GND to V
- 0.3V; All other inputs = V
= +2.3V to +3.6V
= +2.3V to +3.6V
t
WRC) is the time from a valid stop condition of a write sequence to the end of
DD
DD
25
SS
or V
64MB, 128MB, 256MB (x64, SR)
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM UDIMM
SYMBOL
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
t
t
HIGH
LOW
f
WRC
t
t
BUF
SYMBOL
SCL
AA
DH
t
t
t
F
R
I
V
V
V
I
V
I
I
I
DD
LO
SB
DD
OL
LI
IH
IL
MIN
200
100
V
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
DD
MIN
2.3
-1
–
–
–
–
–
x 0.7
MAX
300
400
0.9
0.3
50
10
V
V
DD
DD
UNITS
MAX
3.6
0.4
KHz
10
10
30
ms
2
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
+ 0.5
x 0.3
©2004 Micron Technology, Inc.
NOTES
UNITS
mA
µA
µA
µA
1
2
2
3
4
V
V
V
V