MT9VDDT6472PHG-335D2 Micron Technology Inc, MT9VDDT6472PHG-335D2 Datasheet - Page 13

• Manufacturer Part Number: MT9VDDT6472PHG-335D2
• Description: MODULE SDRAM DDR 512MB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDT6472PHG-335D2

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.4A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 12: I
DDR SDRAM components only;
Notes: 1–5, 8, 10, 12, 47; notes appear on pages 19–22; 0°C
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
t
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT: One device bank; Active-Read-
Precharge; Burst = 2
0mA; Address and control inputs changing once per clock
cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device
banks idle; Power-down mode;
(LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
inputs changing once per clock cycle. V
and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One
device bank; Active-Precharge;
(MIN); DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing once per
clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle; CK =
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One device bank active; Address and control inputs
changing once per clock cycle;
DQS inputs changing twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four bank interleaving READs (BL=4)
with auto precharge with,
Address and control inputs change only during Active READ,
or WRITE commands
RC =
CK =
t
t
RC (MIN);
CK MIN; CKE = HIGH; Address and other control
DD
t
CK =
;
Specifications and Conditions – 128MB
t
RC =
t
CK (MIN); DQ, DM and DQS inputs
t
t
RC (MIN);
RC =
t
0.2V
CK =
t
t
RC = RAS (MAX);
CK =
t
t
RC (MIN);
CK =
t
t
CK (MIN); I
CK (MIN); DQ, DM, and
t
t
CK =
CK (MIN); CKE =
IN
t
CK (MIN); CKE = LOW
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
t
t
= V
REFC =
REFC = 15.625µs
t
t
CK (MIN); I
REF
CK =
for DQ, DQS,
OUT
t
RFC (MIN)
t
t
CK =
CK (MIN);
= 0mA
OUT
t
CK
=
13
T
A
SYMBOL
I
I
I
I
I
I
I
DD 4 W
I
I
DD 3 N
I
DD 5 A
I
I
DD 2 P
DD 2 F
DD 3 P
DD 4 R
+70°C; V
DD 0
DD 1
DD 5
DD 6
DD 7
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
1,125
1,215
1,260
1,260
2,385
3,195
-335
405
225
450
= V
27
45
27
DD
Q = +2.5V ±0.2V
MAX
1,080
1,170
1,125
1,980
2,970
-262
990
405
225
450
27
45
27
©2004 Micron Technology, Inc. All rights reserved.
-26A/
1,080
1,125
1,080
1,980
2,925
-265
945
360
180
405
27
45
18
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ADVANCE
21, 28,
21, 28,
20, 41
20, 41
20, 41
20, 43
24, 43
20, 42
43
44
43
20
9