MT9VDDT6472PHG-335D2 Micron Technology Inc, MT9VDDT6472PHG-335D2 Datasheet - Page 28

• Manufacturer Part Number: MT9VDDT6472PHG-335D2
• Description: MODULE SDRAM DDR 512MB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDT6472PHG-335D2

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.4A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 21: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Table 22: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
NOTE:
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: I
INPUT LEAKAGE CURRENT: V
OUTPUT LEAKAGE CURRENT: V
STANDBY CURRENT:
SCL = SDA = V
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
edge of SDA.
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
DD
- 0.3V; All other inputs = V
OUT
SS
SS
IN
; V
; V
= 3mA
OUT
= GND to V
DDSPD
DDSPD
= GND to V
= +2.3V to +3.6V
= +2.3V to +3.6V
t
WRC) is the time from a valid stop condition of a write sequence to the end of
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
DD
SS
or V
DD
DD
28
200-PIN DDR SDRAM SODIMM
SYMBOL
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SYMBOL
t
t
t
t
t
V
HD:DAT
V
HD:STA
SU:DAT
V
I
SU:STA
SU:STO
V
I
I
t
t
t
I
DD
LO
SB
t
HIGH
DD
OL
LI
LOW
f
WRC
t
t
IH
IL
BUF
SCL
AA
DH
t
t
t
F
R
I
V
DD X
MIN
MIN
2.3
200
100
-1
0.2
1.3
0.6
0.6
1.3
0.6
0.6
–
–
–
–
–
0
0.7
MAX
©2004 Micron Technology, Inc. All rights reserved.
300
400
0.9
0.3
50
10
V
V
DD
DD
MAX
3.6
0.4
10
10
30
UNITS
2
+ 0.5
x 0.3
KHz
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
ADVANCE
NOTES
UNITS
mA
µA
µA
µA
V
V
V
V
1
2
2
3
4