MT9VDDT6472PHG-335D2 Micron Technology Inc, MT9VDDT6472PHG-335D2 Datasheet - Page 21
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MT9VDDT6472PHG-335D2
Manufacturer Part Number
MT9VDDT6472PHG-335D2
Description
MODULE SDRAM DDR 512MB 200SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT9VDDT6472PHG-335D2.pdf
(33 pages)
Specifications of MT9VDDT6472PHG-335D2
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
333MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
512Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.4A
Number Of Elements
9
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
30.
31. READs and WRITEs with auto precharge are not
32. Any positive glitch must be less than 1/3 of the
33. Normal Output Drive Curves:
160
140
120
100
80
60
40
20
b. The variation in driver pull-down current within
d. The variation in driver pull-up current within
c. The full variation in driver pull-up current from
e. The full variation in the ratio of the maximum to
Figure 8: Pull-Down Characteristics
0
0.0
t
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
allowed to be issued until
fied prior to the internal precharge command
being issued.
clock and not more than +400mV or 2.9V, which-
ever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -
300mV or 2.2V, whichever is more positive.
a. The full variation in driver pull-down current
HP min is the lesser of
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure 8,
Pull-Down Characteristics.
minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figure 9, Pull-Up Char-
acteristics
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure 9,
Pull-Up Characteristics.
minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Pull-Down Characteristics.
0.5
1.0
V
V
OUT
OUT
(V)
(V)
t
CL minimum and t
t
RAS(min) can be satis-
1.5
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
2.0
Minimum
t
CH
2.5
21
34. The voltage levels used are derived from a mini-
35. V
36. V
37.
38.
39. During initialization, V
40. The current Micron part operates below the slow-
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
f. The full variation in the ratio of the nominal
0
200-PIN DDR SDRAM SODIMM
0.0
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
pulse width
greater than 1/3 of the cycle rate. V
V
pulse width can not be greater than 1/3 of the
cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
be equal to or less than V
V
even if V
of 42 of series resistance is used between the V
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
Figure 9: Pull-Up Characteristics
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
IL
DD
RPST), or begins driving (
TT
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source voltages
from 0.1V to 1.0V.
(MIN) = -1.5V for a pulse width
and V
may be 1.35V maximum during power up,
t
overshoot: V
DQSCK (MIN) +
DD
DD
0.5
DD
level and the referenced test load. In
/V
Q must track each other.
3ns and the pulse width can not be
DD
Q are 0Vs, provided a minimum
IH
1.0
(MAX) = V
V
DD
t
Q - V
RPRE (MAX) condition.
t
RPRE begin point are not
DD
©2004 Micron Technology, Inc. All rights reserved.
OUT
DD
t
Q, V
t
LZ (MIN) will prevail
(V)
RPRE).
1.5
+ 0.3V. Alternatively,
TT
t
DQSCK (MAX) +
DD
, and V
Q + 1.5V for a
IL
ADVANCE
undershoot:
3ns and the
2.0
REF
must
TT
2.5