MT9HTF6472AY-667D4 Micron Technology Inc, MT9HTF6472AY-667D4 Datasheet - Page 20

• Manufacturer Part Number: MT9HTF6472AY-667D4
• Description: MODULE DDR2 512MB 240-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9HTF6472AY-667D4

• Memory Type: DDR2 SDRAM
• Memory Size: 512MB
• Package / Case: 240-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Other names: 557-1303; MT9HTF6472AY-667D4

RDQS Enable/Disable
Output Enable/Disable
On Die Termination (ODT)
Off-Chip Driver (OCD) Impedance Calibration
Posted CAS Additive Latency (AL)
pdf: 09005aef80e6f860, source: 09005aef80e5b799
HTF9C32_64_128x72AG_2.fm - Rev. C 6/05 EN
RDQS/RDQS# is supported only on RDIMMs using x8 DDR2 SDRAM devices. The RDQS
enable function is defined by bit E11 as shown in Figure 7, Extended Mode Register Defi-
nition, on page 19. When enabled (E11 = 1), RDQS is identical in function and timing to
data strobe DQS during a READ. During a WRITE operation, RDQS is ignored by the
DDR2 SDRAM device.
The OUTPUT enable function is defined by bit E12 as shown in Figure 7, Extended Mode
Register Definition, on page 19. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#,
RDQS, RDQS#) function normally. When disabled (E12 = 1), all DDR2 SDRAM device
outputs (DQs, DQS, DQS#, RDQS, RDQS#) are disabled removing output buffer current.
The OUTPUT disable feature is intended to be used during I
current.
ODT effective resistance R
Figure 7, Extended Mode Register Definition, on page 19. The ODT feature is designed to
improve signal integrity of the memory channel by allowing the DDR2 SDRAM device
controller to independently turn on/off ODT for any or all devices. R
tance values of 75Ω and 150Ω are selectable and apply to each DQ, DQS/DQS#, RDQS/
RDQS#, and DM signals. Additionally, the -667 speed modules offer a third option of
50Ω. Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
The ODT control pin is used to determine when R
ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input
pin are only used during active, active power-down (both fast-exit and slow-exit modes),
and precharge power-down modes of operation. If SELF REFRESH operation is used,
R
SDRAM device. During power-up and initialization of the DDR2 SDRAM device, ODT
should be disabled until the EMR command is issued to enable the ODT feature, at
which point the ODT pin will determine the R
or 1Gb DDR2 SDRAM discrete data sheet for ODT timing diagrams.
The OCD function is not supported and must be set to the default state. e “Initialization”
on page 11, to properly set OCD defaults.
Posted CAS additive latency (AL) is supported to make the command and data bus effi-
cient for sustainable bandwidths in DDR2 SDRAM device. Bits E3–E5 define the value of
AL as shown in Figure 7, Extended Mode Register Definition, on page 19. Bits E3–E5
allow the user to program the DDR2 SDRAM device with a CAS# additive latency of 0, 1,
2, 3, or 4 clocks. Reserved states should not be used as unknown operation or incompat-
ibility with future versions may result.
In this operation, the DDR2 SDRAM device allows a READ or WRITE command to be
issued prior to
cation using this feature would set AL =
mand is held for the time of the additive latency (AL) before it is issued internally to the
DDR2 SDRAM device. READ Latency (RL) is controlled by the sum of the Posted CAS
TT
(
256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 SDRAM UDIMM
EFF
) should always be disabled and the ODT input pin is disabled by the DDR2
t
RCD (MIN) with the requirement that AL ≤
TT
(
EFF
20
) is defined by bits E2 and E6 of the EMR as shown in
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD (MIN) - 1 x
TT
(
EFF
TT
(
) value. Refer to the 256Mb, 512Mb,
EFF
) is turned on and off, assuming
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
t
CK. The READ or WRITE com-
t
RCD(MIN). A typical appli-
DD
RDQS Enable/Disable
characterization of read
TT
effective resis-