MA240017 Microchip Technology, MA240017 Datasheet - Page 60

• Manufacturer Part Number: MA240017
• Description: MODULE PLUG-IN PIC24F16KA102 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA240017

• Accessory Type: Plug-In Module (PIM) - PIC24F16KA102
• Product: Microcontroller Modules
• Data Bus Width: 16 bit
• Core Processor: PIC24F16KA102
• Operating Supply Voltage: 3 V to 3.6 V
• Development Tools By Supplier: Integrated Development Environment, Assembler, ANSI C Compiler
• Processor Series: PIC24F
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC24
• Silicon Core Number: PIC24F
• Silicon Family Name: PIC24FxxKAxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Explorer 16 (DM240001 or DM240002)
• For Use With: DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24F16KA102 FAMILY
REGISTER 7-1:
DS39927B-page 58
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Note 1:
R/W-0, HS
R/W-0, HS
TRAPR
EXTR
2:
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an
0 = An illegal opcode or uninitialized W Reset has not occurred
SBOREN: Software Enable/Disable of BOR bit
1 = BOR is turned on in software
0 = BOR is turned off in software
Unimplemented: Read as ‘0’
DPSLP: Deep Sleep Mode Flag bit
1 = Deep Sleep has occurred
0 = Deep Sleep has not occurred
Unimplemented: Read as ‘0’
PMSLP: Program Memory Power During Sleep bit
1 = Program memory bias voltage remains powered during Sleep
0 = Program memory bias voltage is powered down during Sleep
EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit
1 = WDT is enabled
0 = WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
IDLE: Wake-up from Idle Flag bit
1 = Device has been in Idle mode
0 = Device has not been in Idle mode
R/W-0, HS
R/W-0, HS
IOPUWR
SWR
Address Pointer caused a Reset
RCON: RESET CONTROL REGISTER
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
SWDTEN
R/W-0, HS
SBOREN
R/W-0
(2)
R/W-0, HS
WDTO
U-0
Preliminary
—
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0, HS
SLEEP
(2)
U-0
—
(1)
R/W-0, HS
R/C-0, HS
DPSLP
IDLE
© 2009 Microchip Technology Inc.
x = Bit is unknown
R/W-1, HS
BOR
U-0
—
R/W-1, HS
PMSLP
R/W-0
POR
bit 8
bit 0