C8051T610DB32 Silicon Laboratories Inc, C8051T610DB32 Datasheet - Page 154
![DAUGHT BOARD T610 32TQFP SOCKET](/photos/9/2/90275/c8051t610db32_sml.jpg)
C8051T610DB32
Manufacturer Part Number
C8051T610DB32
Description
DAUGHT BOARD T610 32TQFP SOCKET
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051T610DB32.pdf
(218 pages)
Specifications of C8051T610DB32
Module/board Type
Socket Module - TQFP
Processor To Be Evaluated
C8051T61x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T610DK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1505
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C8051T610/1/2/3/4/5/6/7
SFR Definition 23.1. SCON0: Serial Port 0 Control
SFR Address = 0x98; Bit-Addressable
154
Name S0MODE
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
S0MODE Serial Port 0 Operation Mode.
Unused
Name
MCE0
REN0
RB80
TB80
RI0
TI0
R/W
7
0
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
Unused. Read = 1b, Write = Don’t Care.
Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode:
Mode 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
Mode 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
Receive Enable.
0: UART0 reception disabled.
1: UART0 reception enabled.
Ninth Transmission Bit.
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
Ninth Receive Bit.
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0
interrupt service routine. This bit must be cleared manually by software.
Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
R
6
1
MCE0
R/W
5
0
REN0
R/W
Rev 1.0
4
0
Function
TB80
R/W
3
0
RB80
R/W
2
0
R/W
TI0
1
0
R/W
RI0
0
0
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