CY3687 Cypress Semiconductor Corp, CY3687 Datasheet - Page 15

• Manufacturer Part Number: CY3687
• Description: KIT DEV MOBL-USB FX2LP18
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB HX2LP™r

Specifications of CY3687

• Main Purpose: Interface, USB 2.0 Host/Controller
• Utilized Ic / Part: CY7C68053
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 7. FX2LP18 Pin Descriptions (continued)
Document # 001-06120 Rev *J
56 VFBGA
PORT D
7G
2G
8A
7A
6B
6A
3B
3A
3C
2A
1A
1B
7H
8H
PD0 or
FD[8]
PD1 or
FD[9]
PD2 or
FD[10]
PD3 or
FD[11]
PD4 or
FD[12]
PD5 or
FD[13]
PD6 or
FD[14]
PD7 or
FD[15]
RDY0 or
SLRD
RDY1 or
SLWR
CTL0 or
FLAGA
CTL1 or
FLAGB
CTL2 or
FLAGC
IFCLK
Name
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Input
Input
I/O/Z
O/Z
O/Z
O/Z
Default
(PD0)
(PD1)
(PD2)
(PD3)
(PD4)
(PD5)
(PD6)
(PD7)
N/A
N/A
H
H
H
Z
I
I
I
I
I
I
I
I
[9]
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
RDY0 is a GPIF input signal.
SLRD is the input only read strobe with programmable polarity (FIFOPIN-
POLAR.3) for the slave FIFOs connected to FD[7:0] or FD[15:0].
Multiplexed pin whose function is selected by IFCONFIG[1:0].
RDY1 is a GPIF input signal.
SLWR is the input only write strobe with programmable polarity (FIFOPIN-
POLAR.2) for the slave FIFOs connected to FD[7:0] or FD[15:0].
Multiplexed pin whose function is selected by IFCONFIG[1:0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave FIFO output status flag signal.
Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
Multiplexed pin whose function is selected IFCONFIG[1:0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.
Interface clock, used to synchronous clock data into or out of the slave FIFOs.
IFCLK also serves as a timing reference for all slave FIFO control signals and
GPIF. When internal clocking is used (IFCONFIG.7 = 1) the IFCLK pin can be
configured to output 30 or 48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK
may be inverted, whether internally or externally sourced, by setting the bit
IFCONFIG.4 =1.
Description
CY7C68053
Page 15 of 42
[+] Feedback