SI3232PPT0-EVB Silicon Laboratories Inc, SI3232PPT0-EVB Datasheet - Page 123
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
SI3232PPT0-EVB
Manufacturer Part Number
SI3232PPT0-EVB
Description
BOARD EVAL W/SI3200 INTERFACE
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheet
1.SI3232-FQ.pdf
(128 pages)
Specifications of SI3232PPT0-EVB
Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
Si3232
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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12. Package Outline: 64-Pin eTQFP
Figure 39 illustrates the package details for the Si3232. Table 33 lists the values for the dimensions shown in the
illustration.
Notes:
Symbol
A1
A2
D1
D2
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1982.
3. This package outline conforms to JEDEC MS-026, variant ACD-HD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020B specification for Small Body
A
D
b
c
e
Components.
0.05
0.95
0.17
0.09
4.35
Min
—
Figure 39. 64-Pin Thin Quad Flat Package (TQFP)
Table 33. 64-Pin Package Diagram Dimensions
Millimeters
12.00 BSC.
10.00 BSC.
0.50 BSC.
Nom
1.00
0.22
4.50
—
—
—
Max
1.20
0.15
1.05
0.27
0.20
4.65
Preliminary Rev. 0.96
Symbol
aaa
bbb
ddd
ccc
E1
E2
E
Θ
L
4.35
0.45
Min
—
—
—
—
0 °
Millimeters
12.00 BSC.
10.00 BSC.
Nom
4.50
0.60
3.5 °
—
—
—
—
Max
4.65
0.75
0.20
0.20
0.08
0.08
Si3232
7 °
123
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