SI3232PPT0-EVB Silicon Laboratories Inc, SI3232PPT0-EVB Datasheet - Page 14
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
SI3232PPT0-EVB
Manufacturer Part Number
SI3232PPT0-EVB
Description
BOARD EVAL W/SI3200 INTERFACE
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheet
1.SI3232-FQ.pdf
(128 pages)
Specifications of SI3232PPT0-EVB
Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
Si3232
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Si3232
14
Table 11. Switching Characteristics—PCLK and FSYNC Timing
(V
Parameter
PCLK Period
Valid PCLK Inputs
FSYNC Period
PCLK Duty Cycle Tolerance
PCLK Period Jitter Tolerance
Rise Time, PCLK
Fall Time, PCLK
Setup Time, FSYNC to PCLK Fall
Hold Time, FSYNC to PCLK Fall
FSYNC Pulse Width
Notes:
DD
FSYNC
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
, V
PCLK
DD1
–V
DD4
2
t
=
s u 1
3.13 to 3.47 V, T
A
Figure 2. PCLK, FSYNC Timing Diagram
=
0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, C
Symbol
t
t
t
t
jitter
t
su1
wfs
t
t
dty
t
h1
t
fs
p
r
f
Preliminary Rev. 0.96
t
h 1
Conditions
t
Test
p
t
f s
Min
122
t
40
25
20
—
—
—
—
—
—
—
—
—
—
—
—
—
p
/2
t
1
r
IH –
V
Typ
1.024
1.536
1.544
2.048
4.096
8.192
L
256
512
768
125
I/O –
50
—
—
—
—
—
—
—
=
20 pF)
0.4 V, V
1
125 µs–t
IL
Max
3706
±120
=
60
25
25
—
—
—
—
—
—
—
—
—
—
—
—
0.4 V.
t
1
f
p
Units
MHz
MHz
MHz
MHz
MHz
MHz
kHz
kHz
kHz
µs
ns
ns
ns
ns
ns
ns
ns
%
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