SI5324-EVB Silicon Laboratories Inc, SI5324-EVB Datasheet - Page 16

• Manufacturer Part Number: SI5324-EVB
• Description: BOARD EVALUATION SI5324
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5324-EVB

• Main Purpose: Timing, Clock Multiplier
• Embedded: No
• Utilized Ic / Part: SI5324
• Primary Attributes: 2 Inputs, 2 Outputs
• Secondary Attributes: CML, CMOS, LVDS, LVPECL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Si5324
16
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5324 Register Map.
GND PAD
Pin #
29
28
34
35
36
CKOUT1+
CKOUT2+
Pin Name
CKOUT1–
CKOUT2–
CMODE
GND
GND
I/O
O
O
I
Signal Level
LVCMOS
Supply
Multi
Multi
Output Clock 1.
Differential output clock with a frequency range of 8 kHz to
1.4175 GHz. Output signal format is selected by SFOUT1_REG
register bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive identi-
cal single-ended clock outputs.
Output Clock 2.
Differential output clock with a frequency range of 8 kHz to
1.4175 GHz. Output signal format is selected by SFOUT2_REG
register bits. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive identi-
cal single-ended clock outputs.
Control Mode.
Selects I
0 = I
1 = SPI Control Mode
This pin must not be NC. Tie either high or low.
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Preliminary Rev. 0.3
2
C Control Mode
2
C or SPI control mode for the Si5324.
Description