SI5324-EVB Silicon Laboratories Inc, SI5324-EVB Datasheet - Page 17

• Manufacturer Part Number: SI5324-EVB
• Description: BOARD EVALUATION SI5324
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5324-EVB

• Main Purpose: Timing, Clock Multiplier
• Embedded: No
• Utilized Ic / Part: SI5324
• Primary Attributes: 2 Inputs, 2 Outputs
• Secondary Attributes: CML, CMOS, LVDS, LVPECL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Register
5. Register Map
All register bits that are not defined in this map should always be written with the specified Reset Values. The
writing to these bits of values other than the specified Reset Values may result in undefined device behavior.
Registers not listed, e.g. Register 64, should never be written to.
10
11
19
20
21
22
23
24
25
31
32
33
34
35
36
40
41
42
43
44
45
46
0
1
2
3
4
5
6
7
8
9
FOS_EN
AUTOSEL_REG[1:0]
CKSEL_REG[1:0]
D7
HLOG_2[1:0]
ICMOS[1:0]
FREE_RUN
N1_HS[2:0]
N2_HS[2:0]
SLEEP
D6
BWSEL_REG[3:0]
FOS_THR[1:0]
ALWAYS_ON
HIST_AVG[4:0]
CKOUT_
DHOLD
D5
HLOG_1[1:0]
SFOUT2_REG[2:0}
SQ_ICAL
Preliminary Rev. 0.3
D4
VALTIME[1:0]
NC1_LS[15:8]
NC2_LS[15:8]
NC1_LS[7:0]
NC2_LS[7:0]
N2_LS[15:8]
CK_ACTV_ POL
N2_LS[7:0]
N31[15:8]
CK2_BAD_PIN
N31[7:0]
DSBL2_ REG
D3
CK_PRIOR2[1:0]
CK1_ BAD_ PIN
CK_BAD_ POL
DSBL1_ REG
LOS2_MSK
FOS2_MSK
HST_DEL[4:0]
D2
NC1_LS[19:16]
NC2_LS[19:16]
N2_LS[19:16]
SFOUT1_REG[2:0]
CK1_ACTV_PIN
FOSREFSEL[2:0]
BYPASS_REG
FOS1_MSK
LOS1_MSK
LOCK[T2:0]
LOL_POL
N31[18:16]
N32[18:16]
LOL_PIN
PD_CK2
D1
CK_PRIOR[1:0]
Si5324
CKSEL_PIN
LOSX_MSK
LOL_MSK
INT_POL
PD_CK1
INT_PIN
D0
17