SI5324-EVB Silicon Laboratories Inc, SI5324-EVB Datasheet - Page 55

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SI5324-EVB

Manufacturer Part Number
SI5324-EVB
Description
BOARD EVALUATION SI5324
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI5324-EVB

Main Purpose
Timing, Clock Multiplier
Embedded
No
Utilized Ic / Part
SI5324
Primary Attributes
2 Inputs, 2 Outputs
Secondary Attributes
CML, CMOS, LVDS, LVPECL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
8. Package Outline: 36-Pin QFN
Figure 7 illustrates the package details for the Si5324. Table 6 lists the values for the dimensions shown in the
illustration.
Notes:
Symbol
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
D2
A1
E2
A
D
E
b
e
Components.
0.80
0.00
0.18
3.95
3.95
Min
Millimeters
6.00 BSC
0.50 BSC
6.00 BSC
Figure 7. 36-Pin Quad Flat No-lead (QFN)
Nom
0.85
0.02
0.25
4.10
4.10
Table 6. Package Dimensions
Max
0.90
0.05
0.30
4.25
4.25
Preliminary Rev. 0.3
Symbol
aaa
bbb
ddd
eee
ccc
L
0.50
Min
Millimeters
Nom
0.60
0.10
Max
0.70
0.10
0.08
0.10
0.05
12º
Si5324
55

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