SI5324-EVB Silicon Laboratories Inc, SI5324-EVB Datasheet - Page 27

• Manufacturer Part Number: SI5324-EVB
• Description: BOARD EVALUATION SI5324
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5324-EVB

• Main Purpose: Timing, Clock Multiplier
• Embedded: No
• Utilized Ic / Part: SI5324
• Primary Attributes: 2 Inputs, 2 Outputs
• Secondary Attributes: CML, CMOS, LVDS, LVPECL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Reset value = 0010 1100
Register 19.
Name
Type
Bit
Bit
6:5
4:3
2:0
7
FOS_THR [1:0] FOS_THR [1:0].
VALTIME [1:0] VALTIME [1:0].
FOS_EN
LOCKT [2:0]
FOS_EN
R/W
D7
Name
FOS_EN.
Frequency Offset Enable globally disables FOS. See the individual FOS enables
(FOSx_EN, register 139).
0: FOS disable
1: FOS enabled by FOSx_EN
Frequency Offset at which FOS is declared:
00: ± 11 to 12 ppm (Stratum 3/3E compliant, with a Stratum 3/3E used for REFCLK
01: ± 48 to 49 ppm (SMC)
10: ± 30 ppm (SONET Minimum Clock (SMC), with a Stratum 3/3E used for REFCLK.
11: ± 200 ppm
Sets amount of time for input clock to be valid before the associated alarm is removed.
00: 2 ms
01: 100 ms
10: 200 ms
11: 13 seconds
LOCKT [2:0].
Sets retrigger interval for one shot monitoring phase detector output. One shot is trig-
gered by phase slip in DSPLL. Refer to the Family Reference Manual for more details.
To minimize lock time, the value 001 for LOCKT is recommended.
000: 106 ms
001: 53 ms
010: 26.5 ms
011: 13.3 ms
100: 6.6 ms
101: 3.3 ms
110: 1.66 ms
111: .833 ms
D6
FOS_THR [1:0]
R/W
D5
Preliminary Rev. 0.3
D4
VALTIME [1:0]
R/W
Function
D3
D2
LOCKT [2:0]
R/W
D1
Si5324
D0
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