SI5324-EVB Silicon Laboratories Inc, SI5324-EVB Datasheet - Page 52

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SI5324-EVB

Manufacturer Part Number
SI5324-EVB
Description
BOARD EVALUATION SI5324
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI5324-EVB

Main Purpose
Timing, Clock Multiplier
Embedded
No
Utilized Ic / Part
SI5324
Primary Attributes
2 Inputs, 2 Outputs
Secondary Attributes
CML, CMOS, LVDS, LVPECL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Si5324
6.1. ICAL
The device's registers must be configured for the intended applications. After the part is configured, the part must
perform a calibration procedure when there is a stable clock on the selected CLKINn input. The calibration process
is triggered by writing a "1" to bit D6 in register 136. See the Family Reference Manual for details. In addition, after
a successful calibration operation, changing any of the Registers indicated in Table 4 requires that a calibration be
performed again by the same procedure (writing a "1" to bit D6 in register 136).
52
Address
Table 4. ICAL-Sensitive Registers
10
10
19
19
19
19
25
31
34
40
40
43
46
55
55
11
11
0
0
1
1
2
4
5
7
9
Preliminary Rev. 0.3
CKOUT_ALWAYS_ON
BYPASS_REG
BWSEL_REG
CLKIN1RATE
CLKIN2RATE
FOSREFSEL
DSBL1_REG
DSBL2_REG
CK_PRIOR1
CK_PRIOR2
HIST_DEL
HIST_AVG
FOS_THR
VALTIME
Register
FOS_EN
PD_CK1
PD_CK2
NC1_LS
NC2_LS
ICMOS
LOCKT
N2_HS
N2_LS
N1HS
N31
N32

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