CDB44800 Cirrus Logic Inc, CDB44800 Datasheet - Page 53
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CDB44800
Manufacturer Part Number
CDB44800
Description
BOARD EVAL FOR CS44800 PWM CTRL
Manufacturer
Cirrus Logic Inc
Series
Popguard®r
Specifications of CDB44800
Amplifier Type
Class D
Output Type
8-Channel
Voltage - Supply
20 V ~ 50 V
Operating Temperature
-10°C ~ 70°C
Board Type
Fully Populated
Utilized Ic / Part
CS44800
Description/function
Audio DSPs
Operating Supply Voltage
5 V
Product
Audio Modules
For Use With/related Products
CS44800
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Max Output Power X Channels @ Load
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1532
CDB-44800
CDB-44800
DS632F1
7.5
7.5.1
7.5.2
7.5.3
DIF2
7
Misc. Configuration (address 04h)
Digital Interface Format (DIFX)
Default = 001
Function:
These bits select the digital interface format used for the DAI Serial Port. The required relationship be-
tween the Left/Right clock, serial clock, and serial data is defined by the Digital Interface Format and the
options are detailed in Figures 17 - 22.
AM Frequency Hopping (AM_FREQ_HOP)
Default = 0
Function:
Enables the modulator to alter the PWM switch timings to remove interference when the desired frequen-
cy from an AM tuner is positioned near the PWM switching rate. The PWM modulator circuitry must first
be powered down using the PDN bit in the Clock Configuration and Power Control (address 02h) Register
before this feature can be enabled. There will be a delay following the power-up sequence due to the re-
locking of the SRC. Once this feature is enabled, the output switch rate is divided by 2.25, resulting in a
lowered PWM switch rate. Care should be taken to ensure that:
Freeze Controls (FREEZE)
Default = 0
Function:
This function will freeze the previous output of, and allow modifications to be made to the Master Volume
Control (address 07h-08h), Channel XX Volume Control (address 09h-12h), and Channel Mute (address
13h) registers without the changes taking effect until the FREEZE bit is disabled. To make multiple chang-
es in these control port registers take effect simultaneously, enable the FREEZE bit, make all register
changes, then disable the FREEZE bit.
DIF2
PWM_MCLK / 16 > the upper frequency limit of the AM tuner used
0
0
0
0
1
1
1
DIF1
6
DIF1
0
0
1
1
0
0
1
DIF0
5
Table 5. Digital Audio Interface Formats
DIF0
0
1
0
1
0
1
0
RESERVED
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 16-bit data
Right-Justified, 24-bit data
One-Line mode #1, 20-bit data
One-Line mode #2, 24-bit data
TDM Mode, up to 32-bit data
4
AM_FREQ_HOP
Description
3
FREEZE
2
DEM1
1
Figure
18
17
19
19
20
21
22
CS44800
DEM0
0
53