CDB44800 Cirrus Logic Inc, CDB44800 Datasheet - Page 67
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CDB44800
Manufacturer Part Number
CDB44800
Description
BOARD EVAL FOR CS44800 PWM CTRL
Manufacturer
Cirrus Logic Inc
Series
Popguard®r
Specifications of CDB44800
Amplifier Type
Class D
Output Type
8-Channel
Voltage - Supply
20 V ~ 50 V
Operating Temperature
-10°C ~ 70°C
Board Type
Fully Populated
Utilized Ic / Part
CS44800
Description/function
Audio DSPs
Operating Supply Voltage
5 V
Product
Audio Modules
For Use With/related Products
CS44800
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Max Output Power X Channels @ Load
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1532
CDB-44800
CDB-44800
DS632F1
7.26
7.26.1 GPIO Level/Edge Input Sensitive (GPIOX_L/E)
7.27
7.27.1 GPIO Pin Status (GPIOX_STATUS)
RESERVED
RESERVED
7
7
GPIO Pin Level/Edge Trigger (address 2Eh)
GPIO Status Register (address 2Fh)
Default = 0
Function:
General Purpose Input - This bit defines the GPIO input type (0 = level sensitive, 1 = edge trigger) when
a GPIO pin is configured as an input. The GPIO pin status of an input configured as “edge trigger” is
cleared by reading the GPIO Status Register when not enabled to generate an interrupt (MASK bit equals
0b) and by reset. After a reset this bit defaults to 0b, specifying “level sensitive”.
General Purpose Output - Not Used.
Default = x
Function:
General Purpose Input - Bits in this register are read only when the corresponding GPIO pin is configured
as an input. Each bit indicates the status of the GPIO pin. The corresponding bit of a GPIO input config-
ured as “edge trigger” is cleared by reading the GPIO Status Register. GPIO inputs configured as “level
sensitive” will not be automatically cleared, but will reflect the logic state on the GPIO input. The mask bits
in the GPIO Interrupt Mask Register have no effect on the operation of these status bits.
When a GPIO is un-masked and enabled to generate an interrupt, and is configured as “edge trigger”, a
read operation to this register will clear the status bit and remove the interrupt condition. A read operation
to the Interrupt Status (address 2Ah) (read only) when a GPIO is configured to generate an interrupt con-
dition will not clear any bits in this register.
General Purpose Output - For GPIO pins configured as outputs, these bits are used to control the output
signal level. A 1b written to a particular bit will cause the corresponding GPIO pin to be driven to a logic
high. A 0b will cause a logic low.
GPIO6_STATUS GPIO5_STATUS GPIO4_STATUS GPIO3_STATUS GPIO2_STATUS GPIO1_STATUS GPIO0_STATUS
GPIO6_L/E
6
6
GPIO5_L/E
5
5
GPIO4_L/E
4
4
GPIO3_L/E
3
3
GPIO2_L/E
2
2
GPIO1_L/E
1
1
CS44800
GPIO0_L/E
0
0
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