CDB44800 Cirrus Logic Inc, CDB44800 Datasheet - Page 65

• Manufacturer Part Number: CDB44800
• Description: BOARD EVAL FOR CS44800 PWM CTRL
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r

Specifications of CDB44800

• Amplifier Type: Class D
• Output Type: 8-Channel
• Voltage - Supply: 20 V ~ 50 V
• Operating Temperature: -10°C ~ 70°C
• Board Type: Fully Populated
• Utilized Ic / Part: CS44800
• Description/function: Audio DSPs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS44800
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Max Output Power X Channels @ Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1532; CDB-44800

DS632F1
7.22.2 SRC Lock Interrupt (SRC_LOCK)
7.22.3 Ramp-Up Complete Interrupt (RMPUP_DONE)
7.22.4 Ramp-Down Complete Interrupt (RMPDN_DONE)
7.22.5 Mute Complete Interrupt (Mute_DONE)
7.22.6 Channel Over Flow Interrupt (OVFL_INT)
7.22.7 GPIO Interrupt Condition (GPIO_INT)
Default = 0
Function:
When high, indicates that on all active channels, the sample rate converters have achieved lock. This
interrupt is an edge-triggered event.
If this bit is set to a 1b, indicating a lock condition, and an SRC_UNLOCK condition is detected, then this
bit will be reset to 0b before a read of the Interrupt Status Register. Only the last valid state of the SRC
will be reported.
Default = 0
Function:
When high, indicates that all active channels have completed the configured ramp-up interval.
Default = 0
Function:
When high, indicates that all active channels have completed the configured ramp-down interval.
Default = 0
Function:
When high, indicates that all muted channels have completed the mute cycle-down interval as defined by
the SZC[1:0] bits in the
Default = 0
Function:
When high, indicates that the magnitude of an output sample on one of the channels has exceeded full
scale and has been clipped to positive or negative full scale as appropriate. This bit is the logical OR of
all the bits in the Channel Over Flow Status Register. Read the Channel Over Flow Status Register to
determine which channel(s) had the overflow condition.
Default = 0
Function:
When high, indicates that a transition as configured on one of the un-masked GPIO pins has occurred.
This bit is the logical OR of all the supported un-masked bits in the GPIO Status Register. Read the GPIO
Status Register to determine which GPIO input(s) caused the interrupt condition. The GPIO interrupt is
not removed by reading this register. The GPIO Status Register must be read to clear this interrupt. If the
GPIO input is configured as “edge trigger” the interrupt will clear. If the GPIO input is configured as “level
sensitive”, the interrupt condition will remain as long as the GPIO input remains at the active level.
“Volume Control Configuration (address 06h)” on page
55.
CS44800
65