ADIS16365/PCBZ Analog Devices Inc, ADIS16365/PCBZ Datasheet - Page 9

• Manufacturer Part Number: ADIS16365/PCBZ
• Description: BOARD INTERFACE FOR ADIS16365
• Manufacturer: Analog Devices Inc
• Series: iMEMS®, iSensor™r

Specifications of ADIS16365/PCBZ

• Sensor Type: Accelerometer, Gyroscope, 3 Axis
• Sensing Range: ±17g, ±75°/sec, ±150°/sec, ±300°/sec
• Interface: SPI Serial
• Sensitivity: 3.3mg/LSB, 0.0125 ~ 0.05°/sec/LSB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Embedded: No
• Utilized Ic / Part: ADIS16365
• Silicon Manufacturer: Analog Devices
• Application Sub Type: Accelerometer / Gyroscope
• Kit Application Type: Sensing - Motion / Vibration / Shock
• Silicon Core Number: ADIS16365
• Lead Free Status / RoHS Status: Not applicable / RoHS Compliant
• For Use With: ADISUSBZ - KIT EVAL ADIS W/SOFTWARE USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Not applicable / RoHS Compliant

THEORY OF OPERATION
BASIC OPERATION
The ADIS16360/ADIS16365 are autonomous sensor systems
that start up after they have a valid power supply voltage and
begin producing inertial measurement data at the factory default
sample rate setting of 819.2 SPS. After each sample cycle, the
sensor data is loaded into the output registers, and DIO1 pulses
high, which provides a new data ready control signal for driving
system-level interrupt service routines. In a typical system, a
master processor accesses the output data registers through the
SPI interface, using the connection diagram shown in Figure 9.
Table 6 provides a generic functional description for each pin on
the master processor. Table 7 describes the typical master processor
settings that are normally found in a configuration register and
used for communicating with the ADIS16360/ADIS16365.
Table 6. Generic Master Processor Pin Names and Functions
Pin Name
SS
SCLK
MOSI
MISO
IRQ
Table 7. Generic Master Processor SPI Settings
Processor Setting
Master
SCLK Rate ≤ 2 MHz
SPI Mode 3
MSB First Mode
16-Bit Mode
1
For burst read, SCLK rate ≤ 1 MHz. For low power mode, SCLK rate ≤ 300 kHz.
SYSTEM
PROCESSOR
SPI MASTER
VDD
DOUT
SCLK
Figure 9. Electrical Connection Diagram
DIN
CS
I/O LINES ARE COMPATIBLE WITH
NOTES
1. THE DOUT BIT PATTERN REFLECTS THE ENTIRE CONTENTS OF THE REGISTER IDENTIFIED BY [A6:A0]
2. IF R/W = 1 DURING THE PREVIOUS SEQUENCE, DOUT IS NOT DEFINED.
1
SCLK
IN THE PREVIOUS 16-BIT DIN SEQUENCE WHEN R/W = 0.
MOSI
MISO
3.3V OR 5V LOGIC LEVELS
IRQ
SS
Description
The ADIS16360/ADIS16365 operate as slaves
Normal mode, SMPL_PRD[7:0] ≤ 0x09
CPOL = 1 (polarity), CPHA = 1 (phase)
Bit sequence
Shift register/data length
Function
Slave select
Serial clock
Master output, slave input
Master input, slave output
Interrupt request
D15
R/W
D14
A6
D13
A5
6
3
5
4
7
CS
SCLK
DIN
DOUT
DIO1
D12
A4
10
13
D11
A3
ADIS16360/
ADIS16365
5V
SPI SLAVE
11
14
D10
A2
Figure 11. SPI Communication Bit Sequence
12
15
A1
D9
A0
D8
Rev. D | Page 9 of 20
DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D7
D6
D5
The user registers provide addressing for all input/output
operations on the SPI interface. Each 16-bit register has two
7-bit addresses: one for its upper byte and one for its lower
byte. Table 8 lists the lower byte address for each register, and
Figure 10 shows the generic bit assignments.
READING SENSOR DATA
Although the ADIS16360/ADIS16365 produce data indepen-
dently, they operate as SPI slave devices that communicate with
system (master) processors using the 16-bit segments displayed
in Figure 11. Individual register reads require two of these 16-bit
sequences. The first 16-bit sequence contains the read command
bit ( R /W = 0) and the target register address (A6 to A0); the last
eight bits are “don’t care” bits when requesting a read. The second
16-bit sequence transmits the register contents (D15 to D0) on
the DOUT line. For example, if DIN = 0x0A00, the contents of
the XACCL_OUT register are shifted out on the DOUT line
during the next 16-bit sequence.
The SPI operates in full-duplex mode, which means that the
master processor can read the output data from DOUT while
using the same SCLK pulses to transmit the next target address
on DIN.
DEVICE CONFIGURATION
The user register memory map (see Table 8) identifies configu-
ration registers with either a W or R/W. Configuration commands
also use the bit sequence shown in Figure 11. If the MSB = 1, the
last eight bits (DC7 to DC0) in the DIN sequence are loaded into
the memory address associated with the address bits (A6 to A0).
For example, if DIN = 0xA11F, 0x1F is loaded into Address 0x21
(XACCL_OFF, upper byte) at the conclusion of the data frame.
The master processor initiates the backup function by setting
GLOB_CMD[3] = 1 (DIN = 0xBE04). This command copies
the user registers into their assigned flash memory locations
and requires the power supply to stay within its normal operating
range for the entire 50 ms process. The FLASH_CNT register
provides a running count of these events for monitoring the
long-term reliability of the flash memory.
15
D4
14
D3
13
UPPER BYTE
12
D2
Figure 10. Generic Register Bit Assignments
11
D1
10
D0
9
ADIS16360/ADIS16365
8
7
D15
R/W
6
D14
A6
5
LOWER BYTE
D13
A5
4
3
2
1
0