ATTINY20-EK1 Atmel, ATTINY20-EK1 Datasheet - Page 135

• Manufacturer Part Number: ATTINY20-EK1
• Description: KIT EVAL TOUCH ATTINY20
• Manufacturer: Atmel

Specifications of ATTINY20-EK1

• Sensor Type: *
• Sensing Range: *
• Interface: *
• Sensitivity: *
• Voltage - Supply: *
• Embedded: *
• Utilized Ic / Part: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: TinyAVR
• Kit Contents: Board
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: ATtiny20
• Tool / Board Applications: Microcontroller
• Rohs Compliant: Yes
• Tool Type: Development Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor To Be Evaluated: ATtiny20
• Interface Type: Touch
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.5
16.5.1
8235B–AVR–04/11
Register Description
SPCR – SPI Control Register
Figure 16-4. SPI Transfer Format with CPHA = 1
Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient
time for data signals to stabilize. This is shown in
on page 136
Table 16-2.
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
Bit
0x30
Read/Write
Initial Value
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SPI Mode
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
0
1
2
3
and
SPI Modes
SPIE
R/W
7
0
Table 16-4 on page
Conditions
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
SPE
R/W
6
0
MSB
LSB
DORD
R/W
5
0
Bit 6
Bit 1
136.
MSTR
R/W
4
0
Bit 5
Bit 2
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
Table
CPOL
R/W
3
0
Bit 4
Bit 3
16-2, which is a summary of
CPHA
R/W
Bit 3
Bit 4
2
0
SPR1
R/W
Bit 2
Bit 5
1
0
Trailing eDge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
ATtiny20
SPR0
R/W
Bit 1
Bit 6
0
0
Table 16-3
LSB
MSB
SPCR
135