C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 146

DEV KIT FOR C8051F320/F321

C8051F320DK

Manufacturer Part Number
C8051F320DK
Description
DEV KIT FOR C8051F320/F321
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F320DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F320
Silicon Family Name
C8051F32x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F320, C8051F321
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1260

Available stocks

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Part Number
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Part Number:
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Manufacturer:
SiliconL
Quantity:
4
C8051F320/1
15.4. USB Clock Configuration
USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is
selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock
must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options
are described in Section “13. Oscillators” on page 116. The USB0 clock is selected via SFR CLKSEL (see
Figure 13.5 on Page 124).
Clock Recovery circuitry uses the incoming USB data stream to adjust the internal oscillator; this allows
the internal oscillator (and 4x Clock Multiplier) to meet the requirements for USB clock tolerance. Clock
Recovery should be used in the following configurations:
When operating USB0 as a Low Speed function with Clock Recovery, software must write ‘1’ to the
CRLOW bit to enable Low Speed Clock Recovery. Clock Recovery is typically not necessary in Low Speed
mode.
Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are pres-
ent on the USB network. This mode is not required (or recommended) in typical USB environments.
146
Bit7:
Bit6:
Bit5:
Bits4–0: Reserved. Read = Variable. Must Write = 1001b.
CRE
R/W
Bit7
Full Speed
Low Speed
USB Register Definition 15.5. CLKREC: Clock Recovery Control
CRE: Clock Recovery Enable.
This bit enables/disables the USB clock recovery feature.
0: Clock recovery disabled.
1: Clock recovery enabled.
CRSSEN: Clock Recovery Single Step.
This bit forces the oscillator calibration into ‘single-step’ mode during clock recovery.
0: Normal calibration mode.
1: Single step mode.
CRLOW: Low Speed Clock Recovery Mode.
This bit must be set to ‘1’ if clock recovery is used when operating as a Low Speed USB
device.
0: Full Speed Mode.
1: Low Speed Mode.
Communication Speed
CRSSEN
R/W
Bit6
CRLOW
R/W
Bit5
4x Clock Multiplier
Internal Oscillator/2
R/W
Bit4
USB Clock
Rev. 1.4
R/W
Bit3
Reserved
R/W
Bit2
Internal Oscillator
N/A
4x Clock Multiplier Input
R/W
Bit1
R/W
Bit0
USB Address:
00001001
Reset Value
0x0F

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