C8051F320DK Silicon Laboratories Inc, C8051F320DK Datasheet - Page 248

• Manufacturer Part Number: C8051F320DK
• Description: DEV KIT FOR C8051F320/F321
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F320
• Silicon Family Name: C8051F32x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F320, C8051F321
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1260

C8051F320/1
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Revision 1.2 to Revision 1.3
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Revision 1.3 to Revision 1.4
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248
OCUMENT
Updated document with RoHS compliant information.
Updated Table 3.1, “Global Electrical Characteristics,” on page 28.
Updated package drawings in Section “4. Pinout and Package Definitions” on page 30.
Updated Figure “5.4 10-Bit ADC Track and Conversion Example Timing” on page 44. ADC takes 14
SAR clocks to convert a sample.
Added Max and Min values for Offset and Full Scale Error in Table 5.1, “ADC0 Electrical Characteris-
tics,” on page 54.
Updated Bias Generator specifications in Table 6.1, “Voltage Reference Electrical Characteristics,” on
page 56.
Added Max values for Comparator supply current in Table 7.1, “Comparator Electrical Characteristics,”
on page 66.
Updated Section “8. Voltage Regulator (REG0)” with decoupling and bypass capacitor requirements.
Updated Table 8.1, “Voltage Regulator Electrical Specifications,” on page 68.
Updated how to clear the EA bit in Section “9.3. Interrupt Handler”.
Added Table 11.2, “Flash Security Summary,” on page 109.
Added Section “11.4. Flash Write and Erase Guidelines” on page 110.
Updated Internal Oscillator Suspend Mode behavior in Section “13.1.2. Internal Oscillator Suspend
Mode”.
Updated OSCICN reset value in SFR Definition 13.1. “OSCICN: Internal Oscillator Control” on
page 118.
Corrected maximum SMBus transfer speed in Section “16. SMBus”.
Updated Table 16.4, “SMBus Status Decoding,” on page 184.
- Slave Transmitter (0101 0XX)
- Slave Receiver (0001 00X)
Replaced Tables 17.1 though 17.6 with a single table (Table 17.1, “Timer Settings for Standard Baud
Rates Using The Internal Oscillator,” on page 194).
Updated WCOL bit description in SFR Definition 18.2. “SPI0CN: SPI0 Control” on page 204.
Updated references to IT01CF in SFR Definition 19.1. TCON: Timer Control and SFR
Definition 19.2. TMOD: Timer Mode.
Added Step 7 to Watchdog Timer Usage in Section “20.3.2. Watchdog Timer Usage”.
Changed sample system clock frequencies in Table 20.3, “Watchdog Timer Timeout Intervals
page 239.
Removed references to boundary scan in Section “21. C2 Interface”.
Various formatting fixes.
Removed references to "Boundary Scan" in the C2 chapter.
Updated package drawings to reflect JEDEC-standard nomenclature and supplier variations.
Relaxed maximum VBUS Detection Input Threshold specification in Table 5.1 from 4.0 to 2.9 V.
Updated Table 8.1 on page 68.
Updated Table 15.2 on page 144.
Removed USB Register Definition INMAX.
Removed USB Register Definition OUTMAX.
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