XE8000EV101 Semtech, XE8000EV101 Datasheet
XE8000EV101
Specifications of XE8000EV101
Related parts for XE8000EV101
XE8000EV101 Summary of contents
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... ROM parts are conditioned in reels The XE8801A was previously called, and is the same as the XE8801LC01A. Memory Temperature Package type range ** -40° °C MTP LQFP44 -40° °C ROM die -40° °C* ROM LQFP44 -40° °C ROM MLPQ44 www.semtech.com ...
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... Universal Asynchronous Receiver/Transmitter (UART) Chapter 15 Universal Synchronous Receiver/Transmitter (USRT) Chapter 16 Acquisition Chain Chapter 17 Voltage multiplier Chapter 18 Counters/Timers/PWM Chapter 19 The Voltage Level Detector Chapter 20 XE8801AM - SX8801R Dimensions © Semtech 2005 XE8801A – SX8801R Sensing Machine Data Acquisition with ZoomingADC™ TABLE OF CONTENTS www.semtech.com ...
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... Top schematic 1.1.1 General description 1.1.2 XE88LC01 vs XE88LC01A vs XE8801A vs SX8801R 1.2 Pin map 1.2.1 Bare die of XE8801AM 1.2.2 Bare die of SX8801R 1.2.3 LQFP-44 package 1.3 Pin assignment © Semtech 2005 XE8801A – SX8801R 1-1 1-2 1-2 1-4 1-4 1-4 1-5 1-6 1-7 www ...
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... Port general purpose 8 bit parallel I/O port. The USRT (universal synchronous receiver/transmitter) contains some simple hardware functions in order to simplify the software implementation of a synchronous serial link. The UART (universal asynchronous receiver/transmitter) contains a full hardware implementation of the asynchronous serial link. © Semtech 2005 XE8801A – SX8801R 1-2 www.semtech.com ...
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... REGISTERS RESET RESET BLOCK WD POR RC GENERATION/ OSCIN XTAL MANAGEMENT OSCOUT VREG VREG TEST CONTROLLER 8 DATA REGISTERS IRQ HANDLING EVN HANDLING PORT B PB(7:0) Figure 1-1. Block schematic of the XE8801A circuit. © Semtech 2005 MEMORY B address PORT A U control datain PORT C L dataout L E ...
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... See the RESET chapter for more information. The XE8801A is the same product as the XE88LC01A. Its name was modified when XEMICS was bought by Semtech mid-2005. The SX8801R is the ROM version of the XE8801A. 1.2 Pin map 1 ...
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... PC(5) (118, 843.5) PC(6) (118, 571.4) PC(7) (118, 285.4) PB(0) Figure 1-3. Die dimensions and pin coordinates (in µm). © Semtech 2005 3441 1-5 XE8801A – SX8801R VSS (3323, 3760.6) AC_R(0) (3323, 3475.4) AC_R(1) (3323, 3240.8) AC_A(0) (3323, 3006.2) AC_A(1) (3323, 2771.6) VSS (3323, 2487 ...
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... PB(1) 14 PB(2) 15 PB(3) 16 PB(4) 17 PB(5) 18 PB(6) 19 PB(7) 20 VPP/TEST 21 AC_R(3) 22 AC_R(2) Table 1-1. Bonding plan of the LQFP-44 and MLPQ-44 packages © Semtech 2009 Figure 1-4. LQFP-44 or MLPQ-44 pin map, top view Package Pin name 23 AC_A(7) 24 AC_A(6) 25 AC_A(5) 26 AC_A(4) 27 AC_A(3) 28 AC_A(2) 29 AC_A(1) 30 AC_A(0) ...
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... PA(5) 2 PA(6) 3 PA(7) 4 PC(0) 5 PC(1) 6 PC(2) 7 PC(3) 8 PC(4) 9 PC(5) 10 PC(6) 11 PC(7) 12 PWM0 PB(0) 13 PWM1 PB(1) 14 PB(2) 15 PB(3) 16 PB(4) USRT_S0 17 PB(5) USRT_S1 18 PB(6) UART_Tx 19 PB(7) UART_Rx 20 VPP TEST 21 AC_R(3) 22 AC_R(2) 23 AC_A(7) 24 AC_A(6) 25 AC_A(5) © Semtech 2005 XE8801A – SX8801R I/O configuration ...
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... PA(2) 43 CNTD PA(3) 44 PA(4) Pin map table legend: blue bold: configuration at start up AI: analog input AO: analog output DI: digital input DO: digital output OD: nMOS open drain output PU: pull-up resistor POWER: power supply Table 1-3. Pin description table © Semtech 2005 XE8801A – SX8801R ...
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... Operating range 2.3 Supply configurations 2.3.1 Flash circuit 2.3.2 ROM circuit 2.4 Current consumption 2.5 Operating speed 2.5.1 Flash version 2.5.2 ROM circuit version © Semtech 2005 XE8801A – SX8801R 2-1 2-2 2-2 2-3 2-3 2-3 2-5 2-6 2-6 2-6 www.semtech.com ...
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... The capacitor may be omitted when VREG is connected to VBAT. 2. The capacitor on VMULT is optional. The capacitor has to be present if the multiplier is enabled. The multiplier has to be enabled if VBAT<3.0V. 3. VPP should be left open, connected to VBAT through a resistor or connected directly to VBAT. © Semtech 2005 XE8801A – SX8801R Min. Max. Note -0.3 6 ...
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... In this case, the internal voltage regulator is used in order to maintain a low power consumption independent from the supply voltage. The capacitor on VREG has to be connected at all times (value in Table 2-3) to guarantee proper operation of the device. The capacitor on VMULT has to be connected only when VBAT<3V. © Semtech 2005 Min. Typ. ...
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... Figure 2-4). In this configuration, the circuit can not be used above 3.3V. VBAT VREG VMULT VSS Figure 2-3. Supply voltage connections for high speed operation of the ROM version. © Semtech 2005 2.4V – 5.5V C vreg C vmult 2.15V – 3.3V ...
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... PGA and ADC. The power consumption of the ROM version of the circuit is identical configured as shown in Figure 2-2. In the high speed configuration, the current consumption will increase proportional with VBAT. © Semtech 2005 3.3 VBAT (V) ...
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... Figure 2-6. Guaranteed speed as a function of supply voltage and for different maximal temperatures using the voltage regulator. 2.1.5.2 High speed supply configuration In the high speed supply configuration of Figure 2-3, the guaranteed speed of the circuit is shown in Figure 2-7. © Semtech 2005 85°C 45° ...
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... VBAT (V) Figure 2-7. Guaranteed speed as a function of supply voltage and for three temperature ranges when VREG=VBAT. © Semtech 2005 125°C 2.8 3 3.2 3.4 2-7 XE8801A – SX8801R www.semtech.com ...
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... CPU CONTENTS 3.1 CPU description 3.2 CPU internal registers 3.3 CPU instruction short reference © Semtech 2005 XE8801A – SX8801R 3-1 3-2 3-2 3-4 www.semtech.com ...
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... The program counter (PC bit register that indicates the address of the instruction that has to be executed. The stack ( used to memorise the return address when executing subroutines or interrupt routines. n Instruction memory 22bit Figure 3-1. CPU internal registers © Semtech 2005 CPU core makes it possible to compute program counter stack CPU ...
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... V overflow This flag is used in shift or arithmetic operations. For arithmetic or shift operations with signed numbers overflow or underflow occurs. Table 3-3. Flag description © Semtech 2005 XE8801A – SX8801R 3-3 www.semtech.com ...
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... Cpl2c reg1, reg2 Cpl2c reg Cpl2c reg, eaddr Inc reg1, reg2 Inc reg Inc reg, eaddr Incc reg1, reg2 Incc reg Incc reg, eaddr © Semtech 2005 eaddr Operation PC := addr[15: true then PC := addr[15: true then (n>1 PC+ addr[15:0] n (n>1 PC+ n PC+ addr[15: PC+ ...
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... Z, a Setb reg,#bit[2: Clrb reg,#bit[2: Invb reg,#bit[2: © Semtech 2005 a := reg2-1; if a=hFF then else reg1 a := reg-1; if a=hFF then else reg a := DM(eaddr)-1; if a=hFF then else reg2-(1-C); if a=hFF and C=0 then else reg-(1-C); if a=hFF and C=0 then else ...
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... GT op1>op2 GE op1≥op2 LT op1<op2 LE op1≤op2 Table 3-6. Jump condition description © Semtech 2005 a[ a[ xor V; a[ full; a[ empty a := reg << a[ reg[ DM(eaddr)<<1; a[0] := DM(eaddr)[7] reduces the CPU frequency (divn=nodiv, div2, div4, div8, div16) halts the CPU no operation DM(eaddr) and will simultaneously execute the index operation ...
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... UART (h0050-h0057) 4.2.11 Counter/Timer/PWM registers (h0058-h005F) 4.2.12 Acquisition chain registers (h0060-h0067) 4.2.13 Voltage multiplier (h007C) 4.2.14 Voltage Level Detector registers (h007E-h007F) 4.2.15 RAM (h0080-h027F) © Semtech 2005 XE8801A – SX8801R 4-1 4-2 4-2 4-3 4-4 4-4 4-4 4-5 4-5 4-5 ...
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... The access mode of the different bits (see Table 4-4-1 for code description) 4. The reset source and reset value of the different bits The reset source coding is given in Table 4-4-2. To get a full description of the reset sources, please refer to the reset block chapter. © Semtech 2005 CPU ...
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... Reg00 h0000 Reg01 h0001 Reg02 h0002 Reg03 h0003 Reg04 h0004 Reg05 h0005 Reg06 h0006 Reg07 h0007 Table 4-4-3. Low power data registers © Semtech 2005 Reg00[7:0] rw, xxxxxxxx,- Reg01[7:0] rw,xxxxxxxx,- Reg02[7:0] rw,xxxxxxxx,- Reg03[7:0] rw,xxxxxxxx,- Reg04[7:0] rw,xxxxxxxx,- Reg05[7:0] rw,xxxxxxxx,- Reg06[7:0] rw,xxxxxxxx,- Reg07[/:0] ...
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... Port B (h0028-h002F) Name Address 7 6 RegPBOut h0028 RegPBIn h0029 RegPBDir h002A RegPBOpen h002B RegPBPullup h002C RegPBAna h002D r0 r0 Table 4-4-6. Port B registers © Semtech 2005 EnBusError EnResWD rw,0,cold rw,0,cold r0 r0 ResetBusError ResetfromportA ResetWD ResPad rc, 0, cold rc, 0, cold rc, 0, cold rc,0,cold EnExtClock ...
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... CntIrqA Counter/Timer A (counter block) CntIrqB Counter/Timer B (counter block) CntIrqC Counter/Timer C (counter block) CntIrqD Counter/Timer D (counter block) 128Hz Low prescaler (clock block) 1Hz Low prescaler (clock block) PAEvn[1:0] Port A Table 4-4-9. Event source description © Semtech 2005 PCOut[7:0] rw,00000000,pconf PCIn[7:0] r,-,- PD1Dir[7:0] rw,00000000,pconf ...
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... PAIrq[7:0] Port A UartIrqRx UART reception UartIrqTx UART transmission UrstCond1 USRT condition 1 UsrtCond2 USRT condition 2 VldIrq Voltage level detector IrqAC Acquisition chain end of conversion interrupt Table 4-4-11. Interrupt source description © Semtech 2005 CntIrqA CntIrqC r0 rc1,0,sys rc1,0,sys r0 PAIrq[5] PAIrq[4] 1Hz VldIrq rc1,0,sys ...
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... Name Address 7 6 RegCntA h0058 RegCntB h0059 RegCntC h005A RegCntD h005B RegCntCtrlCk CntDCkSel[1:0] h005C rw,xx,- CntDDownUp CntCDownUp RegCntConfig1 h005D rw,x,- rw,x,- RegCntConfig2 CapSel[1:0] h005E rw,00,sys RegCntOn h005F r0 r0 Table 4-14. Counter/timer/PWM register description. © Semtech 2005 UsrtEnWaitCond1 UsrtWaitS0 rw,0,sys r0 r0 r,0,sys ...
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... Table 4-17. Voltage level detector register description 4.2.15 RAM (h0080-h027F) The 512 RAM bytes can be accessed for read and write operations. The RAM has no reset function. Variables stored in the RAM should be initialised before use since they can have any value at circuit start up. © Semtech 2005 ...
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... System Block 5.1 Overview 5.2 Operating mode © Semtech 2005 XE8801A – SX8801R 5-1 5-2 5-2 www.semtech.com ...
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... The start-up time of the oscillator will then be longer however. Note recommended to insert a NOP instruction after the instruction that sets the circuit in sleep mode because this instruction can be executed when the sleep mode is left using the resetfromportA. © Semtech 2005 XE8801A – SX8801R 5-2 ...
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... Halt instruction ACTIVE Interrupt/event normal mode Figure 5-1. XE8801A and SX8801R operating modes. © Semtech 2005 por por padreset portA reset STAND-BY set bit sleep low current very low current 5-3 XE8801A – SX8801R SLEEP www ...
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... Programmable Port A input combination 6.5.4 Watchdog reset 6.5.5 BusError reset 6.5.6 Sleep mode 6.6 Control register description and operation 6.7 Watchdog 6.8 Start-up and watchdog specifications © Semtech 2005 XE8801A – SX8801R 6-1 6-2 6-2 6-2 6-3 6-4 6-4 6-4 6-4 6-4 6-4 ...
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... ResPadSleep resetcold Table 6-2. RegSysReset register © Semtech 2005 Function enables Sleep mode 0: sleep mode is disabled 1: sleep mode is enabled enables the resetpconf signal when the resetglobal is active 0: resetpconf is disabled 1: resetpconf is enabled enables reset from BusError 0: BusError reset source is disabled 1: BusError reset source is enabled ...
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... Asserted Sleep - (1) For the circuits XE8801AM/XE88LC01AM/SX8801R and XE8805AM/XE88LC05AM (2) For the circuits XE88LC01 and XE88LC05 Table 6-4 Internal reset assertion as a function of the reset source. © Semtech 2005 Function unused Watchdog Key bit 3 Watchdog counter bit 3 Watchdog Key bit 2 Watchdog counter bit 2 ...
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... Note: Several bits might be set or not, if the register was not cleared in between 2 reset occurrences. Write any value in RegSysReset to clear it. Note: When a reset pin wakes up the chip from the sleep mode, ResPad and ResPadSleep bits are equal at 1. © Semtech 2005 bit in the RegSysCtrl register has been set and if the EnResetWD 6-4 XE8801A – ...
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... At start-up of the circuit, the POR (power-on-reset) block generates a reset signal during t software execution after this period (see system chapter). The POR is intended to force the circuit in a correct state at start-up. For precise monitoring of the supply voltage, the voltage level detector (VLD) has to be used. © Semtech 2005 XE8801A – SX8801R 6-5 ...
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... Note: 3) For the circuit versions XE88LC01 and XE88LC05. Gives the time the reset is active after the falling edge of the RESET pin. Note: 4) For the circuit versions XE88LC01A and XE88LC05A. Gives the time the reset is active after the falling edge of the RESET pin. © Semtech 2005 XE8801A – SX8801R Unit Min ...
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... Clock sources 7.5.1 RC oscillator 7.5.2 Xtal oscillator 7.5.3 External clock 7.6 Clock source selection 7.7 RegSysMisc Description 7.8 Prescalers 7.9 32 kHz frequency selector © Semtech 2005 XE8801A – SX8801R 7-1 7-2 7-2 7-2 7-4 7-4 7-4 7-6 7-7 7-8 7-8 7-9 7-9 ...
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... RCOnPA0 2 DebFast 1 OutputCkXtal 0 OutputCpuCk pos. RegSysPre0 7 ResPre © Semtech 2005 rw Reset rw 0 resetsleep Select speed for cpuck, 0=RC, 1=xtal or external clock r 0 resetcold External clock detected, 1=available rw 0 resetcold Enable for external clock, 1=enabled rw 1 resetcold Enable Rcbias (reduces start-up time of RC). ...
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... RcFreqFine[1] 0 RcFreqFine[0] RegSysRcTrim1 RegSysRcTrim2 CkRc RC External 0 Clock 0 1 CkXtal 1 OSCIN Xtal CpuSel EnXtal and not(ExtClk or EnExtClk) © Semtech 2005 rw reset r 00 Unused rw 0 resetcold Reserved rw 0 resetcold Low/high freq. range (low= resetcold RC coarse trim bit resetcold RC coarse trim bit resetcold RC coarse trim bit 1 ...
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... The RcFreqCoarse modifies the frequency of the oscillator by a factor (RcFreqCoarse+1). The figure represents the frequency for 5 different values of the bits RcFreqCoarse: for each value the frequency is multiplied by 2. Incrementing the RcFreqFine code increases the frequency by about 1.4%. The frequency of the oscillator is therefor given by: © Semtech 2005 Mapping in the interrupt manager RegIrqHig(6) RegIrqMid(3) ...
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... Temperature dependence Note 1: this is the frequency tolerance when all trimming codes are 0. Note 2: frequency shift as a function of VBAT with normal regulator function. Note 3: frequency shift as a function of VBAT while the regulator is short-circuited to VBAT. © Semtech 2005 RcFreqFine 0001 0011 min typ ...
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... Keep lines OSCIN and OSCOUT short and insert a VSS line in between them. Connect the crystal package to VSS. No noisy or digital lines near OSCIN or OSCOUT. Insert guards where needed. Respect the board specifications of Table 7-9. © Semtech 2005 Min Typ Max 32768 nominal 8 ...
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... Symbol Description F External EXT frequency PW_1 Pulse 1 width PW_0 Pulse 0 width Table 7-11. External clock specifications. © Semtech 2005 Min Typ 0.5 0.5 0.2 Table 7-9. Board layout specifications. Min Typ ...
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... Bit OutputCkXtal allows to show the Xtal clock on PB[3]. The EnableXtal bit must be set to 1 else PB[3] equals 0 (see port B documentation to set up the Port B). Bit OutputCpuCk allows to show the CpuClock on PB[2] (see Port B documentation). © Semtech 2005 Clock targets Note 1 Cpuck ...
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... A decoder is used to select from the high prescaler the frequency tap that is the closest to 32 kHz to operate the low prescaler when the Xtal is not running. In this case, the RC oscillator frequency of ±50% will also be valid for the low prescaler frequency outputs. © Semtech 2005 XE8801A – SX8801R 7-9 ...
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... IRQ - Interrupt Handler 8.1 Features 8.2 Overview 8.3 Register map © Semtech 2005 XE8801A – SX8801R 8-1 8-2 8-2 8-2 www.semtech.com ...
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... RegIrqHig 7 RegIrqHig[7] 6 RegIrqHig[6] 5 RegIrqHig[5] 4 RegIrqHig[4] 3 RegIrqHig[3] 2 RegIrqHig[2] 1 RegIrqHig[1] 0 RegIrqHig[0] © Semtech 2005 rw reset r 0 resetsystem interrupt #23 (high priority) c1 clear interrupt #23 when 1 is written r 0 resetsystem interrupt #22 (high priority) c1 clear interrupt #22 when 1 is written r 0 resetsystem interrupt #21 (high priority) c1 clear interrupt #21 when 1 is written ...
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... RegIrqEnHig 7 RegIrqEnHig[7] 6 RegIrqEnHig[6] 5 RegIrqEnHig[5] 4 RegIrqEnHig[4] 3 RegIrqEnHig[3] 2 RegIrqEnHig[2] 1 RegIrqEnHig[1] 0 RegIrqEnHig[0] © Semtech 2005 rw reset r 0 resetsystem interrupt #15 (mid priority) c1 clear interrupt #15 when 1 is written r 0 resetsystem interrupt #14 (mid priority) c1 clear interrupt #14 when 1 is written r 0 resetsystem interrupt #13 (mid priority) c1 clear interrupt #13 when 1 is written ...
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... RegIrqEnLow[4] 3 RegIrqEnLow[3] 2 RegIrqEnLow[2] 1 RegIrqEnLow[1] 0 RegIrqEnLow[0] pos. RegIrqPriority 7-0 RegIrqPriority pos. RegIrqIrq 7 IrqHig 1 IrqMid 0 IrqLow © Semtech 2005 rw reset rw 0 resetsystem 1= enable interrupt # resetsystem 1= enable interrupt # resetsystem 1= enable interrupt # resetsystem 1= enable interrupt # resetsystem 1= enable interrupt # resetsystem 1= enable interrupt # resetsystem 1= enable interrupt #9 rw ...
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... Event Handler 9.1 Features 9.2 Overview 9.3 Register map © Semtech 2005 XE8801A – SX8801R 9-1 9-2 9-2 9-2 www.semtech.com ...
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... Register map pos. RegEvn 7 RegEvn[7] 6 RegEvn[6] 5 RegEvn[5] 4 RegEvn[4] 3 RegEvn[3] 2 RegEvn[2] 1 RegEvn[1] 0 RegEvn[0] © Semtech 2005 rw reset r 0 resetsystem event #7 (high priority) c1 clear event #7 when written resetsystem event #6 (high priority) c1 clear event #6 when written resetsystem event #5 (high priority) c1 clear event #5 when written 1 r ...
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... RegEvnEn[5] 4 RegEvnEn[4] 3 RegEvnEn[3] 2 RegEvnEn[2] 1 RegEvnEn[1] 0 RegEvnEn[0] pos. RegEvnPriority 7-0 RegEvnPriority pos. RegEvnEvn 7 EvnHig 0 EvnLow © Semtech 2005 rw reset rw 0 resetsystem 1= enable event # resetsystem 1= enable event # resetsystem 1= enable event # resetsystem 1= enable event # resetsystem 1= enable event # resetsystem 1= enable event # resetsystem 1= enable event #1 rw ...
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... Low Power RAM 10.1 Features 10.2 Overview 10.3 Register map © Semtech 2005 XE8801A – SX8801R 10-1 10-2 10-2 10-2 www.semtech.com ...
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... Reg03 pos. Reg04 7-0 Reg04 pos. Reg05 7-0 Reg05 pos. Reg06 7-0 Reg06 pos. Reg07 7-0 Reg07 © Semtech 2005 rw reset function rw XXXXXXXX low-power data memory Table 10-1: Reg00 rw reset function rw XXXXXXXX low-power data memory Table 10-2: Reg01 rw reset function ...
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... Port A 11.1 Features 11.2 Overview 11.3 Register map 11.4 Interrupts and events map 11.5 Port A (PA) Operation 11.6 Port A electrical specification © Semtech 2005 XE8801A – SX8801R 11-1 11-2 11-2 11-3 11-4 11-4 11-5 www.semtech.com ...
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... PA[0] to PA[3] can be used as clock inputs for the counters/timers/PWM (product dependent) • PA[0] can be used to enable the RC oscillator 11.2 Overview Port general purpose 8 bit wide digital input port, with interrupt capability. Figure 11-1 shows its structure. VBat © Semtech 2005 Port A RegPAPullup 8 RegPADebounce RegPACtrl debounce 0 8 RegPAIn 8 ...
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... PADebounce[7:0] pos. RegPAEdge 7:0 PAEdge[7:0] pos. RegPAPullup 7:0 PAPullup[7:0] pos. RegPARes0 7:0 PARes0[7:0] pos. RegPARes1 7:0 PARes1[7:0] © Semtech 2005 rw reset description r pad PA[7] to PA[0] input value Table 11-1: RegPAIn rw reset description 00000000 r w resetpconf Table 11-2: RegPADebounce rw reset description PA[7] to PA[0] edge configuration ...
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... RegPAEdge. After reset, the rising edge is selected for interrupt generation by default. The interrupt source can be debounced by setting register RegPADebounce. Note: care must be taken when modifying RegPAEdge because this register performs an edge selection. The change of this register may result in a transition which may be interpreted as a valid interruption. © Semtech 2005 Default mapping in the event manager RegEvn[4] ...
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... Port A electrical specification Sym description V Input high voltage INH V Input low voltage INL R Pull-up resistance PU Cin Input capacitance Note 1: this value is indicative only since it depends on the package. Table 11-9. Port A electrical specification. © Semtech 2005 PARes0[x] PAReset[ not(PA[x min typ max unit Comments ...
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... Port B analog configuration 12.5.2 Port B analog function specification 12.6 Port B function capability 12.7 Port B digital capabilities 12.7.1 Port B digital configuration 12.7.2 Port B digital function specification © Semtech 2005 XE8801A – SX8801R 12-1 12-2 12-2 12-2 12-3 12-3 12-3 12-4 12-5 12-5 ...
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... PBOpen[7- resetpconf Pos. RegPBPullup rw 7 –0 PBPullup[ resetpconf © Semtech 2005 reset description in digital mode Pad PB[7-0] output value Table 12-1: RegPBOut reset description in digital mode Pad PB[7-0] input status Table 12-2: RegPBIn reset description in digital mode Pad PB[7-0] direction (0=input) ...
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... When PBAna[ then PBPullup[x] connects the pin to the analog bus. PBDir[x] and PBPOut[x] select which of the 4 analog lines is used. For odd values of x, the selection bits are in the register RegPBOut (see Table 12-8). For even values of x, the selection bits are in the register RegPBDir (see Table 12-9). © Semtech 2005 reset description in digital mode ...
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... Note 4: This is the input capacitance seen on the pin when the pin is connected to an analog line and no other pin is connected to the same analog line. This value is indicative only since it is product and package dependent. © Semtech 2005 PBPullup[x] PB[x] selection on ...
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... Impedance. The internal pull- external pull-up resistor can be used to drive the pin high. Note: Because the P transistor actually exists (this is not a real Open-drain output) the pull-up range is limited to VDD + 0.2V (avoid forward bias the P transistor / diode). © Semtech 2005 XE8801A – SX8801R 12-5 ...
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... Input low voltage INL V Output high voltage OH V Output low voltage OL R Pull-up resistance PU Cin Input capacitance Note 1: this value is indicative only since it depends on the package. © Semtech 2005 min typ max unit Comments 0.7*VBAT VBAT V VSS 0.2*VBAT V VBAT-0.4 VBAT V VSS VSS+0 ...
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... Port C 13.1 Features 13.2 Overview 13.3 Port C (PC) Operation 13.4 Register map 13.5 Port C electrical specification © Semtech 2005 XE8801A – SX8801R 13-1 13-2 13-2 13-2 13-3 13-3 www.semtech.com ...
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... The status of Port C is available in RegPCIn (read only). Reading is always direct - there is no digital debounce function associated with Port C. In case of possible noise on input signals, a software debouncer or an external filter must be realized. By default after reset, Port C is configured as an input port. © Semtech 2005 Port C 8 RegPCOut ...
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... INH V Input low voltage INL V Output high voltage OH V Output low voltage OL Cin Input capacitance Note 1: this value is indicative only since it depends on the package. © Semtech 2005 Rw Reset Description r - pad PC input value Table 13-1 RegPCIn Rw Reset resetpconf pad PC output value Table 13-2 RegPCOut ...
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... Uart on the RC oscillator 14.5.2 Uart on the crystal oscillator 14.6 Function description 14.6.1 Configuration bits 14.6.2 Transmission 14.6.3 Reception 14.7 Interrupt or polling 14.8 Software hints © Semtech 2005 XE8801A – SX8801R 14-1 14-2 14-2 14-2 14-3 14-3 14-3 14-4 14-4 14-4 14-5 14-6 14-6 14-7 www ...
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... UartXTx rw 2-0 UartBR(2:0) rw pos. RegUartTx rw 7-0 UartTx rw © Semtech 2005 Reset 0 resetsystem Select input clock RC/external xtal 0 resetsystem Enable Uart Reception 000 resetsystem RC prescaler selection 0 resetsystem Select parity mode odd even 0 resetsystem Enable parity with parity parity 1 resetsystem Select word length bits bits ...
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... In order to obtain a correct baud rate, the RC oscillator frequency has to be set to one of the frequencies given in the table below. The precision of the obtained baud rate is directly proportional to the frequency deviation with respect to the values in the table. © Semtech 2005 reset description 000000 ...
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... The configuration bits of the Uart serial interface can be found in the registers RegUartCmd and RegUartCtrl. The bit SelXtal is used to select the clock source (see chapter 14.5). The bits UartSelRc and UartBR select the baud rate (see chapter 14.5). The bit UartEnTx is used to enable or disable the transmission. © Semtech 2005 2’457’600 1’843’200 1’228’800 614’ ...
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... UartTxBusy UartTxFull Irq_uart_Tx Asynchronous Transmission (back to back) word 1 write to RegUartTx RegUartTx word 1 reguarttx_shift shift clock Tx UartTxBusy UartTxFull Irq_uart_Tx Figure 14-1. Uart transmission timing diagram. © Semtech 2005 word 1 start b0 b1 word 2 word 2 word 1 start b0 b6/7 stop 14-5 XE8801A – SX8801R b6/7 ...
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... Reception driven by polling: the UartRxFull bit read and checked. When the RegUartRx register contains new data and has to be read before a new word is received. Transmission driven by polling: the UartTxFull bit is to read and checked. When the RegUartTx register is empty and a new word can be written to it. © Semtech 2005 b0 b6/7 parity 14-6 XE8801A – ...
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... The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable Uart reception). 2. When there is an interrupt, jump Read RegUartRxSta and check if there is no error. 4. Read data in RegUartRx data is not equal to End-Of-Line, then jump End of reception. © Semtech 2005 XE8801A – SX8801R 14-7 www.semtech.com ...
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... USRT 15.1 Features 15.2 Overview 15.3 Register map 15.4 Interrupts map 15.5 Conditional edge detection 1 15.6 Conditional edge detection 2 15.7 Interrupts or polling 15.8 Function description © Semtech 2005 XE8801A – SX8801R 15-1 15-2 15-2 15-2 15-3 15-4 15-4 15-4 15-5 www.semtech.com ...
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... The values that are read in the registers RegUsrtS1 and RegUsrtS0 are not necessarily the same as the values that were written in the register. The read value is read back on the circuit pins, not in the registers. Since the outputs are open drain, a value different from the register value may be forced by an external circuit on the circuit pins. © Semtech 2005 rw reset r ...
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... RegUsrtEdgeS0 7 UsrtEdgeS0 r 15.4 Interrupts map interrupt source Irq_cond1 Irq_cond2 © Semtech 2005 rw reset “0000” Unused 0 resetsystem Clock stretching flag (0=no stretching), cleared by writing RegUsrtBufferS1 0 resetsystem Enable stretching on UsrtCond1 detection (0=disable) 0 resetsystem Enable stretching operation (0=disable) 0 resetsystem Enable USRT operation (0=disable) ...
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... In receive mode, there are two possibilities to detect condition the detection of the condition can generate an interrupt or the registers can be polled (reading and checking the RegUsrtCond1 and RegUsrtCond2 registers for the status of USRT communication). © Semtech 2005 Figure 15-1: Condition 1 Figure 15-2: Condition 2 15-4 XE8801A – ...
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... The same can be done in combination with condition 1 detection by setting the UsrtEnWaitCond1 bit. Figure 15-4 shows the conditional clock stretching function which is enabled by setting UsrtEnWaitCond1 UsrtWaitS0 write Reg UsrtBufferS1 Figure 15-4: Conditional stretching (UsrtEnWaitCond1=1) © Semtech 2005 XE8801A – SX8801R 15-5 www.semtech.com ...
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... RegUsrtEdgeS0 is set to one on the same S0 rising edge and is cleared by a read operation of the RegUsrtBufferS1 register. The bit therefor indicates that a new value is present in the RegUsrtBufferS1 which was not yet read UsrtBufferS1 read Reg UsrtBufferS1 UsrtEdgeS0 © Semtech 2005 Figure 15-5: S1 sampling 15-6 XE8801A – SX8801R www.semtech.com ...
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... Power Supply Rejection Ratio............................................................................................................. 16-28 16.9 Application Hints............................................................................................................................... 16-29 16.9.1 Input Impedance ................................................................................................................................. 16-29 16.9.2 PGA Settling or Input Channel Modifications....................................................................................... 16-29 16.9.3 PGA Gain & Offset, Linearity and Noise.............................................................................................. 16-29 16.9.4 Frequency Response .......................................................................................................................... 16-30 16.9.5 Power Reduction................................................................................................................................. 16-31 © Semtech 2005 XE8801A – SX8801R 16-1 www.semtech.com ...
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... A/D converter. The reference voltage can be selected on two different channels. Two offset compensation amplifiers allow for a wide offset compensation range. The programmable gain and offset allow one to zoom small portion of the reference voltage defined input range. © Semtech 2005 f S PGA1 ...
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... RegAcCfg0 7 Start 6:5 SET_NELCONV[1:0] 4:2 SET_OSR[2:0] 1 CONT 0 reserved pos. RegAcCfg1 7:6 IB_AMP_ADC[1:0] 5:4 IB_AMP_PGA[1:0] 3:0 ENABLE[3:0] © Semtech 2005 register name RegAcOutLsb RegAcOutMsb RegAcCfg0 RegAcCfg1 RegAcCfg2 RegAcCfg3 RegAcCfg4 RegAcCfg5 Table 16-1: AC registers rw reset description 00000000 r resetsystem Table 16-2: RegAcOutLsb rw reset ...
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... Fine gain programming up to 1'000V/V is possible. In addition, the last two stages provide programmable offset. Each amplifier can be bypassed if needed. The output of the PGA stages is directly fed to the analog-to-digital converter (ADC), which converts the signal V into digital. IN,ADC © Semtech 2005 rw reset description resetsystem ...
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... Note: Over-sampled converters are operated with a sampling frequency f 1'000 times the input signal bandwidth). The sampling frequency to throughput ratio is large (typically 10-500). These converters include digital decimation filtering. They are mainly used for high resolution, and/or low-to-medium speed applications. © Semtech 2005 (Eq. 1) IN,ADC ⋅ ...
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... ENABLE: (rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i=1,2,3). PGA stages that are disabled are bypassed. • FIN: (rw) These bits set the sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency, the sampling frequency is given as: 00 © Semtech 2005 Bit Position ...
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... Note that the flag is set at the effective start of the conversion. Since the ADC is generally synchronized on a CONV lower frequency clock than the CPU, there might be a small delay (max. 1 cycle of the ADC sampling frequency) between the writing of the START or CONT bits and the appearance of BUSY flag. © Semtech 2005 ...
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... AC_A(6) 10111 AC_A(7) Similarly, the reference voltage is chosen among two differential channels (V AC_R(3)-AC_R(2)) as shown in Table 16-12. The selection bit is VMUX. The reference inputs V (common-mode) can the power supply range. (RegAcCfg5[0]) © Semtech 2005 and reference voltage V IN (Eq. 3) (Eq. 4) AMUX[4:0] V ...
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... PGA3: fine gain and offset tuning All gain and offset settings are realized with ratios of capacitors. The user has control over each PGA activation and gain, as well as the offset of stages 2 and 3. These functions are examined hereafter. © Semtech 2005 ENABLE[3:0] Block ...
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... The first stage can have a buffer function (unity gain) or provide a gain of 10 (see Table 16-14). The voltage V the output of PGA1 is: = ⋅ ( where GD is the gain of PGA1 (in V/V) controlled with the bit PGA1_GAIN. 1 © Semtech 2005 PGA3 Gain PGA3_GAIN[6:0] GD (V/V) 3 0000000 0 0000001 1/12(=0.083) ... ... 0000110 6/12 ... ...
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... PGA gain is defined as: = ⋅ ⋅ TOT and the total PGA offset is ⋅ GDoff GDoff GD GDoff TOT 3 3 © Semtech 2005 (V) (Eq. 6) (V) (Eq. 7) REF (Eq. 8) ⋅ (V) (Eq REF (V/V) (Eq. 10) (V/V) (Eq. 11) 2 16-11 XE8801A – SX8801R of the ADC is related IN,ADC www.semtech.com ...
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... The word FIN[1:0] is used to select the sampling frequency f RC-based frequency f can be chosen. For FIN = "11", sampling frequency is about 8kHz. Additional information RCEXT on oscillators and their control can be found in the clock block documentation. Table 16-19 Sampling frequency settings (f © Semtech 2005 . ELCONV elementary incremental conversions and a final ELCONV (Eq. 12) ...
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... Elementary Conversions As mentioned previously, the whole conversion sequence is made of a set of N conversions. This number is set with the word SET_NELC[1:0] in power of 2 steps (see Table 16-21) given by: SET_NELC ELCONV © Semtech 2005 (-) (Eq. 13) Over-Sampling Ratio OSR (-) 000 8 001 16 010 32 011 ...
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... The theoretical resolution of the ADC, without considering thermal noise, is given by: = ⋅ log ( OSR ) log ( ELCONV Figure 16-6 Resolution vs. SET_OSR[2:0] and SET_NELC[2:0] SET_OS R [2:0] 000 001 010 011 100 101 110 111 Table 16-22 Resolution vs. SET_OSR[2:0] and SET_NELC[1:0] settings © Semtech 2005 # of Elementary Conversions N (-) ELCONV (Bits) (Eq. 15 SET_NELC ...
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... The ADC output code is a 16-bit word in two's complement format (see Table 16-24). For input voltages outside the range, the output code is saturated to the closest full-scale value (i.e. 0x7FFF or 0x8000). For resolutions smaller than 16 bits, the non-significant bits are forced to the values shown in Table 16-25. The output code, expressed in LSBs, corresponds to: © Semtech 2005 (s) (Eq. 16 ...
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... Table 16-25. Last forced LSBs in conversion output registers for resolution settings smaller than 16 bits (n < 16) (RegAcOutMsb[7:0] & RegAcOutLsb[7:0]) © Semtech 2005 1 (LSB) (Eq.17) ⎞ OSR 1 ⎟ ⎟ ⋅ ⋅ (LSB) (Eq. 18) REF ...
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... DD • RC frequency f = 2MHz, sampling frequency f RC • Offsets GDOff = GDOff 2 • Power operation: normal (IB_AMP_ADC[1:0] = IB_AMP_PGA[1:0] = '11') • Resolution: for bits: OSR = 32 and N for bits: OSR = 512 and N © Semtech 2005 (V) (Eq. 19) OSR (V) (Eq. 20 ADC PGA Max. f IB_AMP_PGA Bias Bias [1:0] [kHz] ...
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... Throughput Rate (Continuous Mode), 1/T CONV Nbr of Initialization Cycles, N INIT Nbr of End Conversion Cycles, N END PGA Stabilization Delay DIGITAL OUTPUT ADC Output Data Coding © Semtech 2005 = +5V, GND = 0V +5V REF = GDOff = 0. Power operation: normal (IB_AMP_ADC[1:0] = IB_AMP_PGA[1: For resolution bits: OSR = 512 and N ...
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... Bias currents in PGAs and ADC set to 3/4 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘10’, IB_AMP_ADC[1:0] = ‘10’. (18) Bias currents in PGAs and ADC set to 1/2 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘01’, IB_AMP_ADC[1:0] = ‘01’. (19) Bias currents in PGAs and ADC set to 1/4 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘00’, IB_AMP_ADC[1:0] = ‘00’. © Semtech 2005 VALUE UNITS ...
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... Increasing the gain further up to 1000 will further increase the linearity since the signal becomes very small in the first two stages. The signal is full scale at the output of stage 3 and as shown in Figure 16-9 to Figure 16-12, this stage has very good linearity. © Semtech 2005 XE8801A – SX8801R 16-20 ...
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... Figure 16-9 Integral non-linearity of the ADC and with gain of 1 (PGA1 and PGA2 disabled, PGA3=1, Figure 16-10 Integral non-linearity of the ADC and gain of 2 (PGA1 and PGA2 disabled, PGA3=2 Figure 16-11 Integral non-linearity of the ADC and gain of 5 (PGA1 and PGA2 disabled, PGA3=5, © Semtech 2005 XE8801A – SX8801R reference voltage of 5V) ...
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... Figure 16-12 Integral non-linearity of the ADC and gain of 10 (PGA1 and PGA2 disabled, PGA3=10, Figure 16-13 Integral non-linearity of the ADC and gain of 20 (PGA1 and PGA2=10, PGA3=2, reference © Semtech 2005 XE8801A – SX8801R reference voltage of 5V) voltage of 5V) 16-22 www.semtech.com ...
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... Figure 16-15 Integral non-linearity of the ADC and gain of 100 (PGA1=10 and PGA3=10, PGA2 disabled, 16.8.3.2 Differential non-linearity The differential non-linearity is generated by the ADC. The PGA does not add differential non-linearity. Figure 16-16 shows the differential non-linearity. © Semtech 2005 XE8801A – SX8801R reference voltage of 5V) reference voltage of 5V) 16-23 ...
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... Standard deviation at ADC output (LSB) Output rms noise (µV) Note: see noise model of Figure 16-18 and equation Eq. 21. Table 16-27 PGA noise measurements ( bits, OSR = 512, N © Semtech 2005 should result in a constant output code. However, because of circuit noise, the ⋅ + ⋅ ...
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... Moreover, the tolerances between the different stages are not correlated and the probability to get the maximal error in the same direction in all stages is very low. Finally, these gain errors can be calibrated by the software at the same time with the gain errors of the sensor for instance. © Semtech 2005 80 60 ...
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... IB_AMP_PGA [1:0] and IB_AMP_ADC [1:0]. (In Figure 16-22, IB_AMP_PGA/ADC[1:0] = '11', '10', '00' for f = 500, 250, 62.5kHz respectively.) S Quiescent current consumption vs. temperature is depicted in Figure 16-23, showing a relative increase of nearly 40% between -45 and +85°C. Figure 16-24 shows the variation of quiescent current consumption for different © Semtech 2005 > 1. ELCONV NORMALIZED TO 25°C 0.2 0.1 ...
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... Temperature [°C] (a) Figure 16-23 (a) Absolute and (b) relative change inquiescent current consumption vs. temperature © Semtech 2005 800 700 PGA1, 2 & ADC 600 500 PGA1 & ADC 400 PGA1 + ADC 300 200 No PGAs, ADC only 100 2.5 3.0 3 ...
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... Figure 16-25 shows power supply rejection ratio (PSRR and 5V supply voltage, and for various PGA gains. PSRR is defined as the ratio (in dB) of voltage supply change ( the change in the converter output (in V). PSRR depends on both PGA gain and supply voltage V Figure 16-25 Power supply rejection ratio (PSRR) © Semtech 2005 PGA2 PGA1 PGA3 ...
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... For the lowest noise, set the highest possible gain on the first (front) PGA stage used in the chain. For example application where a gain needed, set the gain of PGA2 to 10, set the gain of PGA3 to 2. © Semtech 2005 GAIN =5 GAIN = 10 GAIN = 20 GAIN =100 ...
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... For example, consider a 5Hz-bandwidth, 16-bit sensing system where 50Hz line rejection is needed. Using the above equation and the plots below, we set the 4th notch for N = 50Hz. The sampling frequency is then calculated as f also good attenuation of 50Hz harmonics. © Semtech 2005 = − (Hz) ...
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... Use lower bias currents in the PGAs and the ADC using the control words IB_AMP_PGA[1:0] and IB_AMP_ADC[1:0]. (This reduces the maximum sampling frequency according to Table 16-26.) 5) Reduce internal RC oscillator frequency and/or sampling frequency. Finally, remember that power reduction is typically traded off with reduced linearity, larger noise and slower maximum sampling speed. © Semtech 2005 1 ELCONV 0.8 ...
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... Vmult (Voltage Multiplier) 17.1 Features 17.2 Overview 17.3 Control register 17.4 External component © Semtech 2005 XE8801A – SX8801R 17-1 17-2 17-2 17-2 17-2 www.semtech.com ...
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... Table 17-1. RegVmultCfg0 17.4 External component When the multiplier is enabled, a capacitor has to be connected to the VMULT pin. If the multiplier is disabled, the pin may remain floating. Capacitor on VMULT © Semtech 2005 XE8801A – SX8801R Function enable of the vmult ‘1’ : enabled ‘0’ : disabled system clock division factor ‘ ...
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... Block schematic 18.6 General counter registers operation 18.7 Clock selection 18.8 Counter mode selection 18.9 Counter / Timer mode 18.10 PWM mode 18.11 Capture function © Semtech 2005 XE8801A – SX8801R 18-1 18-2 18-2 18-2 18-4 18-4 18-5 18-5 18-6 18-7 18-8 18-9 www ...
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... Note: When writing to RegCntA or RegCntB, the processor writes the counter comparison values. When reading these locations, the processor reads back either the actual counter value or the last captured value if the capture mode is active. bit RegCntC 7-0 CounterC 7-0 CounterC © Semtech 2005 rw reset r xxxxxxxx w xxxxxxxx Table 18-1. RegCntA rw ...
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... CntPWM1 0 CntPWM0 bit RegCntConfig2 7-6 CapSel(1:0) 5-4 CapFunc(1:0) 3-2 Pwm1Size(1:0) 1-0 Pwm0Size(1:0) bit RegCntOn 7 CntDEnable 2 CntCEnable 1 CntBEnable 0 CntAEnable © Semtech 2005 rw reset r xxxxxxxx w xxxxxxxx Table 18-4. RegCntD rw reset Table 18-5. RegCntCtrlCk rw Reset rw x Counter down counting (0=down Counter down counting (0=down) ...
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... Block schematic ck128 ckrcext/4 ckrcext PA(0) PA(1) ck1k ck32k PA(2) PA(3) Figure 18-1: Counters/timers block schematic © Semtech 2005 Mapping in the Mapping in the event interrupt manager RegIrqHigh(4) RegIrqLow(5) RegIrqHigh(3) RegIrqLow(4) Table 18-9. Interrupt and event mapping. RegCntA (write) Counter A RegCntB (write) ...
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... Table 18-10 gives the correspondence between the binary codes used for the configuration bits CntACkSel(1:0), CntBCkSel(1:0), CntCCkSel(1:0) or CntDCkSel(1:0) and the clock source selected respectively for the counters CntXCkSel(1: Table 18-10: Clock sources for counters and D © Semtech 2005 Clock source for CounterA CounterB CounterC Ck128 CkRc/4 CkRc PA(0) ...
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... CntDDownUp). The mapping of the interrupt sources IrqC and IrqD and the PWM output on PB(1) in these The switching between different modes must be done while the concerned counters are stopped. While switching capture mode on and off, unwanted interrupts can appear on the interrupt channels concerned by this mode change. © Semtech 2005 Counter A Counter B IrqA ...
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... This interrupt is additional to the interrupt which has already been generated when the counter reached the zero or the target value. © Semtech 2005 Counter C Counter D ...
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... RegCntX registers. They are high when the counter contents are smaller or equal to these PWM code values. The PWM resolution is always 8 bits when the counters used for the PWM signal generation are not cascaded. PWM0Size(1:0) and PWM1Size(1:0) in the RegCntConfig2 register are used to set the PWM resolution for the © Semtech 2005 3 2 ...
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... The capture condition is user defined by selecting either internal capture signal sources derived from the prescaler or from the external PA(2) or PA(3) ports. Both counters use the same capture condition. © Semtech 2005 Resolution 11 ...
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... It must be noted that when counters A and B are cascaded, the capture might happen at different cycles for the A and B registers. This is due to the asynchronous relationship between counter and capture clock and to the fact that the capture condition detection is independent for A and B counters. © Semtech 2005 CapFunc Selected condition ...
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... VLD (Voltage Level Detector) 19.1 Features 19.2 Overview 19.3 Register map 19.4 Interrupt map 19.5 VLD operation © Semtech 2005 XE8801A – SX8801R 19-1 19-2 19-2 19-2 19-2 19-2 www.semtech.com ...
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... The VLD is controlled by VldRange, VldTune and VldEn. VldRange selects the voltage range to be detected, while VldTune is used to fine-tune this voltage level in 8 steps. VldEn is used to enable (disable) the VLD with a 1(0) value respectively. When disabled, the block dissipates no power. © Semtech 2005 reset function 0000 ...
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... VLD is enabled, a maskable interrupt request is sent if the voltage level falls below the threshold. One can also poll the VLD and monitor the actual measurement result by reading the VldResult bit of the RegVldStat. This result is only valid as long as the VldValid bit is ‘1’. An interrupt is generated on each rising edge of VldResult. © Semtech 2005 XE8801A – SX8801R min typ ...
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... Physical Dimensions CONTENTS 20.1 LQFP type package 20.2 Die XE8801AM 20.3 Die SX8801R © Semtech 2005 XE8801A – SX8801R 20-1 20-2 20-2 20-3 www.semtech.com ...
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... VSS 52 1555 PC(4) 52 1275 PC(5) 52 995 PC(6) 52 715 PC(7) 52 435 bottom pads PB(0) 398 47 © Semtech 2005 0.10 0.37 0.8 2 large plus 20-30 um due to the saw channel. Zero coordinate is at bottom 2 . Pad surface is xxx. pin X pin Y [um] [um] pin name top pads ...
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... PB(5) 1790 118 PB(6) 2067 118 PB(7) 2344 118 TEST 2735 118 VSS 2971 118 AC_R(3) 3155 118 © Semtech 2005 pin X pin name [um] AC_R(0) 3958 AC_R(1) 3958 AC_A(0) 3958 AC_A(1) 3958 VSS 3958 AC_A(2) 3958 AC_A(3) 3958 AC_A(4) 3958 ...
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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech. assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range ...