XE8000EV101 Semtech, XE8000EV101 Datasheet - Page 127

• Manufacturer Part Number: XE8000EV101
• Description: EVAL BOARD FOR XE8801AMI027LF
• Manufacturer: Semtech
• Type: MCUr

Specifications of XE8000EV101

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: XE88LC01AMI027
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

counters A and B or C and D respectively when they are in cascaded mode. The different possible resolutions in
cascaded mode are shown in Table 18-13. Choosing a 16 bit PWM code higher than the maximum value that can
be represented by the number of bits chosen for the resolution, results in a PWM output which is always tied to 1.
The period of the PWM signal is given by the formula:
The duty cycle ratio DCR of the PWM signal is defined as:
DCR can be selected between 0 % and
DCR in % in function of the RegCntX content(s) is given by the relation:
The 16-bit capture register is provided to facilitate frequency measurements. It provides a safe reading mechanism
for the counters A and B when they are running. When the capture function is active, the processor does not read
anymore the counters A and B directly, but instead reads shadow registers located in the capture block. An
interrupt is generated after a capture condition has been met when the shadow register content is updated. The
capture condition is user defined by selecting either internal capture signal sources derived from the prescaler or
from the external PA(2) or PA(3) ports. Both counters use the same capture condition.
© Semtech 2005
18.11 Capture function
Small PWM code
Large PWM code
Table 18-13: Resolution selection in cascaded PWM mode
PwmXsize(1:0)
Figure 18-3: PWM modulation examples
11
10
01
00
2
resolution
2
resolution
DCR
Tper
−
DCR =
=
1
T
*
100
llarge
100
=
18-9
2
2
*
resolution
Tper
resolution
f
RegCntX
%.
Th
ckcnt
T
Resolution
lsmall
T
T
16 bits
14 bits
12 bits
10 bits
hlarge
per
T
hsmall
XE8801A – SX8801R
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