DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 1238

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Appendix A Electrical Characteristics
A.6.1.2
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V
the PORF bit in the CRG flags register has not been set.
A.6.1.3
When external reset is asserted for a time greater than PW
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.6.1.4
Out of stop the controller can be woken up by an external interrupt. A clock quality check as after POR is
performed before releasing the clocks to the system.
If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and
SCME = 1), the system will resume operation in self-clock mode after t
A.6.1.5
The recovery from pseudo stop and wait is essentially the same since the oscillator is not stopped in both
modes. The controller can be woken up by internal or external interrupts. After t
the interrupt vector.
1238
DD35
SRAM Data Retention
External Reset
Stop Recovery
Pseudo Stop and Wait Recovery
is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
MC9S12XE-Family Reference Manual , Rev. 1.23
RSTL
the CRG module generates an internal
fws
.
wrs
the CPU starts fetching
Freescale Semiconductor