DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 268

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6 Interrupt (S12XINTV2)
6.1.4
Figure 6-1
6.2
The XINT module has no external signals.
268
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Peripheral
Interrupt Requests
Wake up
XGATE
XGATE
Requests
External Signal Description
(Up to 108 Channels)
shows a block diagram of the XINT module.
One Set Per Channel
Block Diagram
Decoder
Priority
RQST
To XGATE Module
Non I Bit Maskable
Vector
ID
IRQ Channel
Channels
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 6-1. XINT Block Diagram
XGATE
Interrupts
INT_XGPRIO
PRIOLVL2
PRIOLVL1
PRIOLVL0
Interrupt
Requests
RQST
PRIOLVLn
INT_XGPRIO = XGATE Interrupt Priority
IVBR
IPL
= bits from the channel configuration
in the associated configuration register
XGATE Request Route,
Priority Level
= Interrupt Vector Base
= Interrupt Processing Level
Wake Up
CPU
IVBR
Address
Vector
Freescale Semiconductor
New
IPL
Current
IPL