DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 152

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.59
2.3.60
152
Address 0x0266
Address 0x0267
Write: Anytime.
Write: Anytime.
Read: Anytime.
Field
PIEH
Field
PIFH
Reset
Reset
7-0
7-0
W
W
R
R
Port H interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port H.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
Port H interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSH register. To clear this flag, write logic level 1 to the corresponding bit in the PIFH register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
PIEH7
PIFH7
Port H Interrupt Enable Register (PIEH)
Port H Interrupt Flag Register (PIFH)
0
0
7
7
PIEH6
PIFH6
0
0
6
6
Figure 2-57. Port H Interrupt Enable Register (PIEH)
Figure 2-58. Port H Interrupt Flag Register (PIFH)
Table 2-55. PPSP Register Field Descriptions
Table 2-56. PPSP Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
PIEH5
PIFH5
0
0
5
5
PIEH4
PIFH4
0
0
4
4
Description
Description
PIEH3
PIFH3
3
0
3
0
PIEH2
PIFH2
0
0
2
2
Access: User read/write
Access: User read/write
Freescale Semiconductor
PIEH1
PIFH1
0
0
1
1
PIEH0
PIFH0
0
0
0
0
(1)
(1)