DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 668

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
17.3.0.5
Read: Anytime
Write: Anytime
17.3.0.6
Read: Anytime
Write: Anytime (write to clear)
668
Module Base + 0x0004
Module Base + 0x0005
PMUX[7:0]
PINTE[7:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
Field
7:0
7:0
W
W
R
R
PINTE7
PTF7
PIT Multiplex Bits for Timer Channel 7:0 — These bits select if the corresponding 16-bit timer is connected to
micro time base 1 or 0. If PMUX is modified, the corresponding 16-bit timer is immediately switched to the other
micro time base.
0 The corresponding 16-bit timer counts with micro time base 0.
1 The corresponding 16-bit timer counts with micro time base 1.
PIT Time-out Interrupt Enable Bits for Timer Channel 7:0 — These bits enable an interrupt service request
whenever the time-out flag PTF of the corresponding PIT channel is set. When an interrupt is pending (PTF set)
enabling the interrupt will immediately cause an interrupt. To avoid this, the corresponding PTF flag has to be
cleared first.
0 Interrupt of the corresponding PIT channel is disabled.
1 Interrupt of the corresponding PIT channel is enabled.
PIT Interrupt Enable Register (PITINTE)
PIT Time-Out Flag Register (PITTF)
0
0
7
7
PINTE6
PTF6
0
0
6
6
Figure 17-7. PIT Interrupt Enable Register (PITINTE)
Figure 17-8. PIT Time-Out Flag Register (PITTF)
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 17-6. PITINTE Field Descriptions
Table 17-5. PITMUX Field Descriptions
PINTE5
PTF5
5
0
5
0
PINTE4
PTF4
0
0
4
4
Description
Description
PINTE3
PTF3
0
0
3
3
PINTE2
PTF2
2
0
2
0
PINTE1
Freescale Semiconductor
PTF1
0
0
1
1
PINTE0
PTF0
0
0
0
0