C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 296

• Manufacturer Part Number: C8051F930DK
• Description: KIT DEV C8051F920,F921,F930,F931
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930DK

• Contents: Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F920, F921, F930, F931
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1473

C8051F93x-C8051F92x
25.3.3. Comparator 1/External Oscillator Capture Mode
The Capture Mode in Timer 3 allows either Comparator 1 or the external oscillator period to be measured
against the system clock or the system clock divided by 12. Comparator 1 and the external oscillator
period can also be compared against each other.
Setting TF3CEN to 1 enables the Comparator 1/External Oscillator Capture Mode for Timer 3. In this
mode, T3SPLIT should be set to 0, as the full 16-bit timer is used.
When Capture Mode is enabled, a capture event will be generated either every Comparator 1 rising edge
or every 8 external clock cycles, depending on the T3XCLK1 setting. When the capture event occurs, the
contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL)
and the TF3H flag is set (triggering an interrupt if Timer 3 interrupts are enabled). By recording the differ-
ence between two successive timer capture values, the Comparator 1 or external clock period can be
determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the capture
clock to achieve an accurate reading.
For example, if T3ML = 1b, T3XCLK1 = 0b, and TF3CEN = 1b, Timer 3 will clock every SYSCLK and cap-
ture every Comparator 1 rising edge. If SYSCLK is 24.5 MHz and the difference between two successive
captures is 350 counts, then the Comparator 1 period is:
350 x (1 / 24.5 MHz) = 14.2 µs.
This mode allows software to determine the exact frequency of the external oscillator in C and RC mode or
the time between consecutive Comparator 0 rising edges, which is useful for detecting changes in the
capacitance of a Touch Sense Switch.
296
E xternal C lock / 8
E xtern al C lock / 8
C om parato r 1
S Y S C LK / 1 2
C om p arator 1
S Y S C LK
T 3X C LK [1:0]
T 3X C LK 1
X 0
01
11
0
1
Figure 25.9. Timer 3 Capture Mode Block Diagram
M
H
T
3
M
0
1
T
3
L
C K C O N
M
T
2
H
M
T
2
L
M
T
1
T F 3 C E N
M
T
0
S
C
A
1
T R 3
S
C
A
0
Rev. 1.1
C apture
T C LK
T M R 3R L L T M R 3 R LH
T M R 3 L
T M R 3H
T 3 X C L K 1
T 3 X C L K 0
T F 3C E N
T 3S P LIT
T F 3 L E N
T F 3H
T F 3L
T R 3
Inte rrupt