C8051F930DK Silicon Laboratories Inc, C8051F930DK Datasheet - Page 314

• Manufacturer Part Number: C8051F930DK
• Description: KIT DEV C8051F920,F921,F930,F931
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F930DK

• Contents: Target Board, Power Adapter, USB Debug Adapter, Cables, Batteries, and Software
• Processor To Be Evaluated: C8051F930
• Processor Series: C8051F9xx
• Data Bus Width: 8 bit
• Interface Type: I2C, UART, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 0.9 V to 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F920, F921, F930, F931
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1473

C8051F93x-C8051F92x
SFR Definition 26.2. PCA0MD: PCA Mode
SFR Page = 0x0; SFR Address = 0xD9
314
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
Reset
Name
Bit
3:1
Type
7
6
5
4
0
Bit
CPS[2:0] PCA Counter/Timer Pulse Select.
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
WDLCK
Unused
WDTE
Name
CIDL
ECF
CIDL
R/W
7
0
PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
Watchdog Timer Enable.
If this bit is set, PCA Module 2 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 2 enabled as Watchdog Timer.
Watchdog Timer Lock.
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
Unused.
Read = 0b, Write = don't care.
These bits select the timebase source for the PCA counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
110: Reserved
111: Reserved
PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
WDTE
R/W
1
6
WDLCK
R/W
5
0
Rev. 1.1
R
4
0
Function
CPS2
R/W
3
0
CPS1
R/W
2
0
CPS0
R/W
1
0
ECF
R/W
0
0