C8051T630DK Silicon Laboratories Inc, C8051T630DK Datasheet - Page 118
![KIT DEV FOR C8051T630 FAMILY](/photos/9/23/92351/c8051t630dk_sml.jpg)
C8051T630DK
Manufacturer Part Number
C8051T630DK
Description
KIT DEV FOR C8051T630 FAMILY
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051T630DK
Contents
Board, daughter boards, power adapter, cables, documentation and software
Processor To Be Evaluated
C8051T63x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T630, T631, T632, T633, T634 and T635 MCUs
For Use With
336-1465 - BOARD SOCKET DAUGHTER 20-QFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1464
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C8051T630/1/2/3/4/5
SFR Definition 20.2. XBR1: Port I/O Crossbar Register 1
SFR Address = 0xE2
20.5. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0 or P1. A soft-
ware controlled value stored in the PnMATCH registers specifies the expected or normal logic values of P0
and P1. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer match the soft-
ware controlled value. This allows Software to be notified if a certain change or pattern occurs on P0 or P1
input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which P0 and P1 pins should be compared
against the PnMATCH registers. A Port mismatch event is generated if (P0 & P0MASK) does not equal
(P0MATCH & P0MASK) or if (P1 & P1MASK) does not equal (P1MATCH & P1MASK).
118
Name WEAKPUD
Reset
1:0 PCA0ME[1:0] PCA Module I/O Enable Bits.
Bit
Type
7
6
5
4
3
2
Bit
WEAKPUD
Unused
XBARE
Name
ECIE
T1E
T0E
R/W
7
0
Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
PCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
Unused. Read = 0b; Write = Don’t Care.
00: All PCA I/O unavailable at Port pins.
01: CEX0 routed to Port pin.
10: CEX0, CEX1 routed to Port pins.
11: CEX0, CEX1, CEX2 routed to Port pins.
XBARE
R/W
6
0
R/W
T1E
5
0
Rev. 1.0
T0E
R/W
4
0
Function
ECIE
R/W
3
0
R
2
0
R/W
PCA0ME[1:0]
1
0
R/W
0
0
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