DK-EMB-3C120N Altera, DK-EMB-3C120N Datasheet - Page 31

• Manufacturer Part Number: DK-EMB-3C120N
• Description: KIT DEV EMB CYCLONE III EDITION
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-EMB-3C120N

• Contents: Board, Cables, CD(s), USB-Blaster™, Power Supply
• Architecture: PLD/FPGA
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III
• Rohs Compliant: Yes
• For Use With/related Products: EP3C120
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2589

Chapter 6: Board Test System
Using the Board Test System
September 2010 Altera Corporation
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:
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Error Control
The Error control controls display data errors detected during analysis and allow you
to insert errors:
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Number of Addresses to Write and Read
The Number of addresses to write and read control determines the number of
addresses to use in each iteration of reads and writes. Valid values range from 8 to
8,192.
Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
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■
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Read and Write Control
The Read and write control specifies the type of transactions to analyze. The
following transaction types are available for analysis:
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Write, Read, and Total performance bars—show the percentage of maximum
theoretical data rate that the requested transactions are able to achieve.
Write(MBps), Read(MBps), and Total(MBps)—show the number of bytes of data
analyzed per second. For DDR2 top design, the data bus is 40-bits wide and the
frequency is 300 MHz double data rate, equating to a theoretical maximum
bandwidth of 1500 MBps. For DDR2 bottom design, the data bus is 32-bits wide
and the frequency is 300 MHz double data rate, equating to a theoretical
maximum bandwidth of 1200 MBps.
Detected errors—displays the number of data errors detected in the hardware.
Inserted errors—displays the number of errors inserted into the transaction
stream.
Insert Error—inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
Clear—resets the Detected errors and Inserted errors counters to zeros.
PRBS—selects pseudo-random bit sequences.
Memory—selects a generic data pattern stored in the on-chip memory of the
Cyclone III device.
Math—selects data generated from a simple math function within the FPGA
fabric.
Write then read—selects read and write transactions for analysis.
Read only—selects read transactions for analysis.
Write only—selects write transactions for analysis.
Cyclone III FPGA Development Kit User Guide
6–11