DK-EMB-3C120N Altera, DK-EMB-3C120N Datasheet - Page 33

• Manufacturer Part Number: DK-EMB-3C120N
• Description: KIT DEV EMB CYCLONE III EDITION
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-EMB-3C120N

• Contents: Board, Cables, CD(s), USB-Blaster™, Power Supply
• Architecture: PLD/FPGA
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III
• Rohs Compliant: Yes
• For Use With/related Products: EP3C120
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2589

Introduction
Power Design Example
Table 7–1. Four Input Button Functionality
September 2010 Altera Corporation
User Push
User_PB0
User_PB1
User_PB2
User_PB3
Button
FPGA Pin
AC12
AA12
AD7
AH3
One of the main features of the Cyclone III FPGA device is its low power
consumption. You can measure the power used by the 3C120 FPGA device on the
Cyclone III development board for various conditions with a power design example
provided with the kit.
With the power design example you can control the amount of logic utilized in the
FPGA, the clock frequency, and the number of I/Os used, and measure the effect on
power used by the Cyclone III device.
The power design example uses a replicated module, stamp.v, that contains
combinational logic, randomly filled ROMs, multiplier blocks, and shift registers that
change with every clock cycle. The frequency and resource states indicated in
Table 7–2
design used. As compiled, the full example design uses the following FPGA
resources:
■
■
■
■
■
■
■
■
■
Table 7–1
power design example. The on-board 50-MHz oscillator provides the input clock
(i_clk, PIN_AH15).
Total logic elements: 111,673 / 119,088 (94%)
Total combinational functions: 12,293 / 119,088 (10%)
Dedicated logic registers: 104,192 / 119,088 (87%)
Total registers: 104,192
Total pins: 165 / 532 (31%)
Total virtual pins: 0
Total memory bits: 2,490,368 / 3,981,312 (63%)
Embedded multiplier 9-bit elements: 576 / 576 (100%)
Total phase-locked loops (PLLs): 1/4 (25%)
and
describes the functionality of the four user push buttons that control the
Toggle
Toggle
Toggle
Reset
Type
Table 7–3 on page
Resets the demo to the beginning, i_nrst
Advances the design example to the next higher frequency,
i_nfreq_next
Advances the design example to the next higher resource utilization,
i_nperc_next
Enables the outputs to toggle, i_noutput_ena
7–2, respectively, represent the percent of the full
7. Power Measurement
Description
Cyclone III FPGA Development Kit User Guide