DK-EMB-3C120N Altera, DK-EMB-3C120N Datasheet - Page 10

KIT DEV EMB CYCLONE III EDITION

DK-EMB-3C120N

Manufacturer Part Number
DK-EMB-3C120N
Description
KIT DEV EMB CYCLONE III EDITION
Manufacturer
Altera
Series
Cyclone® IIIr
Type
FPGAr

Specifications of DK-EMB-3C120N

Contents
Board, Cables, CD(s), USB-Blaster™, Power Supply
Architecture
PLD/FPGA
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Cyclone
Silicon Core Number
EP3C
Silicon Family Name
Cyclone III
Rohs Compliant
Yes
For Use With/related Products
EP3C120
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2589

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DK-EMB-3C120N
Manufacturer:
Altera
Quantity:
135
Part Number:
DK-EMB-3C120N
Manufacturer:
ALTERA
0
Devices
Stratix III L FPGA Features
1
2
8
This is the base core logic register count. The ALM can support three registers when used in LUTREG mode, which increases the total register count by an additional 50 percent.
The size of the MLAB ROM is twice the size of the MLAB RAM.
ALMs
Equivalent LEs
Registers
M9K memory blocks
M144K memory blocks
MLAB memory (Kb)
Embedded memory (Kb)
18-bit x 18-bit multipliers
Speed grades
(fastest to slowest)
Global clock networks
Regional clock networks
Periphery clock networks
PLLs/unique outputs
Design security
Configuration file size (Mb)
HardCopy series device support
Others
I/O voltage levels
supported (V)
I/O standards supported
Emulated LVDS channels,
1,100 Mbps
LVDS channels, 1,600 Mbps
(receive/transmit)
Embedded DPA circuitry
Series and differential OCT
Memory devices supported
Altera Product Catalog
1
2
2011
www.altera.com
EP3SL50
47,500
19,000
38,000
1,836
56/56
4/34
108
297
216
104
48
22
56
6
SSTL-18 (I and II), SSTL-15 (I and II), SSTL-2 (I and II), 1.5-V HSTL (I and II),
LVDS, LVPECL, Differential SSTL-18, Differential SSTL-2, Differential HSTL,
EP3SL70
27,000
67,500
54,000
2,214
56/56
4/34
150
422
288
104
22
48
56
6
1.8-V HSTL (I and II), PCI, PCI-X 1.0, LVTTL, LVCMOS
DDR3, DDR2, DDR, QDR II, RLDRAM II, SDR
Stratix III L FPGAs (1.1 V, 0.9 V)
Programmable Power Technology
EP3SL110
107,500
42,600
85,200
4,203
88/88
8/68
275
672
288
208
12
48
47
88
1.2, 1.5, 1.8, 2.5, 3.3
-2, -3, -4
16
3
3
3
3
EP3SL150
142,500
113,600
56,800
5,499
88/88
8/68
355
891
384
208
16
48
47
88
EP3SL200
198,900
159,120
112/112
79,560
12/96
1,250
9,396
468
576
208
112
36
88
66
EP3SL340
135,200
338,000
270,400
132/132
16,272
1,040
2,110
12/96
576
208
120
137
48
88

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