DK-EMB-3C120N Altera, DK-EMB-3C120N Datasheet - Page 46

• Manufacturer Part Number: DK-EMB-3C120N
• Description: KIT DEV EMB CYCLONE III EDITION
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-EMB-3C120N

• Contents: Board, Cables, CD(s), USB-Blaster™, Power Supply
• Architecture: PLD/FPGA
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III
• Rohs Compliant: Yes
• For Use With/related Products: EP3C120
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2589

Licensing
Development Kits
When you’re ready to ship your product, you’ll need the Nios II core
license. This royalty-free license never expires and allows you to target
your processor design on any Altera FPGA. The Embedded IP Suite is
a value bundle that contains licenses of the Nios II processor IP core,
DDR1/2 Memory Controller IP core, Triple Speed Ethernet (TSE) MAC IP
core, and the NicheStack TCP/IP Network Stack, Nios II Edition software.
Go to page 50 for information about embedded development kits.
Nios II Embedded Processors
Hardware Development Tools
CPU Core Options
The Nios II processor family has three CPU core options with a common 32-bit instruction set architecture, binary code compatibility,
and the same software design suite. Choose the CPU appropriate for your designs, create multi-core systems to scale performance, or
break up software applications into simpler tasks.
*
• Quartus II design software
• SOPC Builder system integration tools
• SignalTap II embedded logic analyzer plug-in for Nios II processor
• System console for low-level debug of SOPC Builder systems
Embedded Processing
44
The Nios II/e processor is now available for free. No license is required.
Nios II Processor Family Members
Description
Pipeline
Multiplier
Branch prediction
Instruction cache
Data cache
Custom instructions
Altera Product Catalog
Features
•
2011
Optimized for maximum
performance; optional memory
management unit (MMU)
6 stage
1 cycle
Dynamic
Configurable
Configurable
Up to 256
Nios II/f (Fast) Processor
•
www.altera.com
Balanced cost and performance
5 stage
3 cycle
Static
Configurable
None
Up to 256
Nios II/s (Standard) Processor
Nios II C2H Compiler
Right-click to convert your ANSI-C
code into hardware accelerators in the
FPGA using the Nios II C2H Acceleration
Compiler. Accelerate Nios II embedded
software performance from 10X to 70X
without increasing clock frequency.
The tool automates the creation and
integration of hardware accelerators,
reducing development time from weeks
to minutes.
Optimized for minimum logic usage
1 stage
Emulated in software
None
None
None
Up to 256
Nios II/e (Economy) Processor*