DK-EMB-3C120N Altera, DK-EMB-3C120N Datasheet - Page 57

• Manufacturer Part Number: DK-EMB-3C120N
• Description: KIT DEV EMB CYCLONE III EDITION
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-EMB-3C120N

• Contents: Board, Cables, CD(s), USB-Blaster™, Power Supply
• Architecture: PLD/FPGA
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III
• Rohs Compliant: Yes
• For Use With/related Products: EP3C120
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2589

Product and Vendor Name
HD FIFO Modules
Averlogic
Broadcast Video Card
Bitec
Quad Video Board
Bitec
HDMI Receiver/Transmitter
Microtronix
Quad Link LVDS Interface
Microtronix
CX4 to HSMC Adapter
MorethanIP
Daughtercard
Daughtercard
Daughtercard
Daughtercard
Daughtercard
Daughtercard
Device
Description
This board is designed for evaluating the AL460A HD-FIFO. It has two
embedded AL460A-7-PBF (or AL460A-13-PBF) devices operating in
parallel, expanding the bus width to 32 bits. Control signals and data bus
signals are available on two 50-pin connectors. A separate adaptor board
(HSMC interface) is available for connecting the module directly to a
Cyclone III FPGA starter kit.
This card is designed for professional video equipment developers. The
dual ASI/SD-SDI interfaces allow access to industry-standard video
transport signals. Based on the latest adaptive cable equalizers and
drivers, the ASI/SDI interfaces provide excellent noise immunity up to cable
lengths of 350 meters. A VCXO allows precise synchronization to incoming
ASI signals. A DVB-T reference design using the Bitec BVDC daughtercard
and a Cyclone III FPGA Development Kit is available.
This board is based on the Texas Instruments TVP5154 quad video decoder.
The analog video inputs include composite video and S-video. Video
output is based on the Chrontel CH7010B device, enabling single-link DVI,
component analog, and composite analog outputs. The device accepts
digital, parallel video data, and clocking from the host FPGA via the HSMC
connector, which configures and monitors the device over an I
DVI output connector and mini-DIN output connector are provided.
This daughtercard interfaces a HDMI receiver and transmitter to your
Altera FPGA development kit using the HSMC expansion connector. The
receiver also supports an analog component video (YCbCr) interface. The
card uses the Analog Device AD9889 HDMI Transmitter and AD9880 HDMI
Receiver to support HDTV formats up to 1080p at 60 Hz. The receiver
offers the flexibility of both an analog interface and an HDMI receiver
integrated on a single chip.
This daughtercard supports receive and transmit LVDS links, each
consisting of five data channels and one clock for a total of 48 LVDS
channels. The standard configuration of 20 TX + 4 clk and 20 RX + 2 clk,
is capable of supporting LCD display panels up to 1080p at 100/120 Hz.
Onboard LVDS termination resistors can be removed to convert receiver
channels into transmitters as required to support 12- or 14-bit color
applications. It is used for capturing LVDS video data, connecting to a
camera link interface, or for connecting to LCD panels using LVDS,
Mini-LVDS, RSDS, and PPDS low-voltage panel interface signaling.
This is a passive daughtercard for 10GbE CX-4 copper interconnect
prototyping. It features a four-lane differential 3.125-Gbps connector
(CX-4) for 10GbE IEEE 802.3ak, a 160-pin HSMC to the main
board, and compatibility with Stratix II GX mother boards that use
HSMC connectors.
Altera and Partner Development Kits
Altera Product Catalog
•
2011
Development Kits
•
www.altera.com
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