AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 610

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.7.4
32099F–11/2010
Resistive Touch Screen Sequencer
Figure 26-3. Resistive Touch Screen Pin Connections
The Resistive Touch Screen Sequencer is responsible for applying voltage to the resistive touch
screen films as described in
output value of the ADP and AD pins. This allows the Resistive Touch Screen Sequencer to add
a voltage gradient on one film while keeping the other film floating so a touch can be measured.
The Resistive Touch Screen Sequencer will when measuring the vertical position, apply VDD
and GND to the pins connected to X
measurement of Y
non ideal pad drivers, the actual voltage of X
VDD and GND can be used in the contact point calculation to increase accuracy. See second
formula in
When the vertical values are converted the same setup is applies for the second axes, by setting
X
details.
P
and X
M
Section
in tristate mode and applying VDD and GND to Y
Analog Pin Output Enable (MR.APOE) == 1
Analog Pin Output Enable (MR.APOE) == 0
P
26.7.2.
can proceed without interference. To compensate for ADC offset errors and
Y
Y
M
M
X
X
Section
M
M
P
26.7.2. This is done by controlling the output enable and the
and X
M
X
P
X
. The Y
P
P
and X
Y
Y
P
P
P
M
and Y
is measured as well, so the real values for
AT32UC3L016/32/64
M
P
and Y
pins are put in tristate mode so the
NC
NC
AD
AD
AD
AD
AD
M
AD
AD
AD
DP
DP
DP
DP
. Refer to
tspo+0
tspo+3
tspo+0
tspo+3
tspo+1
tspo+1
tspo+2
tspo+2
0
1
0
1
Section 26.8.3
610
for