AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 831

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

35.4.2
35.4.3
32099F–11/2010
FLASHCDW
HMATRIX
3. RETS behaves incorrectly when MPU is enabled
1. Flash selfprogramming may fail in one wait state mode
2. Chip Erase
3. Fuse Programming
4. Wait 500ns before reading from the flash after switching read mode
5. VERSION register reads 0x100
1. In the PRAS and PRBS registers, the MxPR fields are only two bits
RETS behaves incorrectly when MPU is enabled and MPU is configured so that system
stack is not readable in unprivileged mode.
Fix/Workaround
Make system stack readable in unprivileged mode, or return from supervisor mode using
rete instead of rets. This requires:
1. Changing the mode bits from 001 to 110 before issuing the instruction. Updating the
mode bits to the desired value must be done using a single mtsr instruction so it is done
atomically. Even if this step is described in general as not safe in the UC technical reference
manual, it is safe in this very specific case.
2. Execute the RETE instruction.
Writes in flash and user pages may fail if executing code located in the address space
mapped to the flash and if the flash controller is configured in one wait state mode (the Flash
Wait State bit in the Flash Control Register (FCR.FWS) is 1).
Fix/Workaround
Solution 1: Configure the flash controller in zero wait state mode (FCR.FWS=0).
Solution 2: Configure the HMATRIX master 1 (CPU Instruction) to use the unlimited burst
length transfer mode (MCFG1.ULBT=0) and the HMATRIX slave 0 (FLASHCDW) to use the
maximum slot cycle limit (SCFG0.SLOT_CYCLE=255).
When performing a chip erase, the device may report that it is protected (IR=0x11) and that
chip erase failed, even if the chip erase was successful.
Fix/Workaround
Perform a reset before any further read and programming.
Programming of fuses does not work.
Fix/Workaround
Do not program fuses. All fuses will be erased during chip erase command.
After switching between normal read mode and high-speed read mode, the application must
wait at least 500ns before attempting any access to the flash.
Fix/Workaround
Solution 1: Make sure that the appropriate instructions are executed from RAM, and that a
waiting-loop is executed from RAM waiting 500ns or more before executing from flash.
Solution 2: Execute from flash with a clock with period longer than 500ns. This guarantees
that no new read access is attempted before the flash has had time to settle in the new read
mode.
The VERSION register reads 0x100 instead of 0x102.
Fix/Workaround
None.
AT32UC3L016/32/64
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