ADSP-3PARCBF548E02 Analog Devices Inc, ADSP-3PARCBF548E02 Datasheet - Page 44
![KIT DEV STARTER BF548](/photos/9/25/92500/adsp-3parcbf548e02_kit_sml.jpg)
ADSP-3PARCBF548E02
Manufacturer Part Number
ADSP-3PARCBF548E02
Description
KIT DEV STARTER BF548
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
DSPr
Specifications of ADSP-3PARCBF548E02
Contents
Board, Cables, CD, Headset with Microphone, Module, Power Supply
For Use With/related Products
ADSP-BF548
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 44 of 100
- Download datasheet (4Mb)
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Asynchronous Memory Read Cycle Timing
Table 28
on Page 45
tions for synchronous and for asynchronous ARDY.
Table 28. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
1
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and ARE.
SDAT
HDAT
SARDY
HARDY
DO
HO
and
describe asynchronous memory read cycle opera-
Table 29 on Page 45
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Setup Before the Falling Edge of CLKOUT
ARDY Hold After the Falling Edge of CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
DATA 15–0
ADDR19–1
CLKOUT
ABE1–0
ARDY
AMSx
AOE
ARE
t
DO
and
2 CYCLES
Figure 13. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
SETUP
Figure 13
1
1
t
DO
and
Rev. C | Page 44 of 100 | February 2010
PROGRAMMED READ
Figure 14
ACCESS 4 CYCLES
t
SARDY
t
HARDY
ACCESS EXTENDED
t
SARDY
3 CYCLES
t
HARDY
t
SDAT
1 CYCLE
t
HO
HOLD
t
HDAT
Min
5.0
0.8
5.0
0.0
0.3
t
HO
Max
6.0
Unit
ns
ns
ns
ns
ns
ns
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