ADSP-3PARCBF548E02 Analog Devices Inc, ADSP-3PARCBF548E02 Datasheet - Page 64

• Manufacturer Part Number: ADSP-3PARCBF548E02
• Description: KIT DEV STARTER BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: DSPr

Specifications of ADSP-3PARCBF548E02

• Contents: Board, Cables, CD, Headset with Microphone, Module, Power Supply
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Serial Peripheral Interface (SPI) Port—Master Timing
Table 45
Table 45. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
SSPIDM
HSPIDM
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPIDM
HDSPIDM
and
CPHA = 1
CPHA = 0
Figure 38
SPIxSELy
(OUTPUT)
(OUTPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
SPIxMOSI
(OUTPUT)
SPIxMISO
SPIxSCK
(INPUT)
(INPUT)
Data Input Valid to SPIxSCK Edge (Data Input Setup)
SPIxSCK Sampling Edge to Data Input Invalid
SPIxSELy Low to First SPIxSCK Edge
SPIxSCK High Period
SPIxSCK Low Period
SPIxSCK Period
Last SPIxSCK Edge to SPIxSELy High
Sequential Transfer Delay
SPIxSCK Edge to Data Out Valid (Data Out Delay)
SPIxSCK Edge to Data Out Invalid (Data Out Hold)
describe SPI port master operations.
t
SSPIDM
t
SDSCIM
t
HSPIDM
t
SPICLM
Figure 38. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. C | Page 64 of 100 | February 2010
t
SPICHM
t
HDSPIDM
t
HDSPIDM
t
DDSPIDM
t
SPICLK
t
DDSPIDM
t
SSPIDM
t
HDSM
Min
9.0
–1.5
2t
2t
2t
4t
2t
2t
–1.0
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
t
HSPIDM
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
t
SPITDM
Max
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns