ADSP-3PARCBF548E02 Analog Devices Inc, ADSP-3PARCBF548E02 Datasheet - Page 47
![KIT DEV STARTER BF548](/photos/9/25/92500/adsp-3parcbf548e02_kit_sml.jpg)
ADSP-3PARCBF548E02
Manufacturer Part Number
ADSP-3PARCBF548E02
Description
KIT DEV STARTER BF548
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
DSPr
Specifications of ADSP-3PARCBF548E02
Contents
Board, Cables, CD, Headset with Microphone, Module, Power Supply
For Use With/related Products
ADSP-BF548
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 47 of 100
- Download datasheet (4Mb)
Table 31. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
S = number of programmed setup cycles, WA = number of programmed write access cycles.
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and AWE.
DANW
HAA
DDAT
ENDAT
DO
HO
ARDY Negated Delay from AMSx Asserted
ARDY Asserted Hold After AWE Negated
DATA15–0 Disable After CLKOUT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
DATA 15–0
ADDR19–1
CLKOUT
ABE1–0
AMSx
ARDY
AWE
Figure 16. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
2 CYCLES
2
SETUP
t
t
2
ENDAT
DO
Rev. C | Page 47 of 100 | February 2010
t
DANW
WRITE ACCESS
PROGRAMMED
2 CYCLES
1
t
DO
EXTENDED
2 CYCLES
ACCESS
t
HO
t
HAA
1 CYCLE
HOLD
t
DDAT
t
HO
Min
0.0
0.0
0.3
Max
(S + WA – 2) × t
6.0
6.0
SCLK
Unit
ns
ns
ns
ns
ns
ns
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