C8051F326-TB Silicon Laboratories Inc, C8051F326-TB Datasheet - Page 70

• Manufacturer Part Number: C8051F326-TB
• Description: BOARD PROTOTYPING W/C8051F326
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F326-TB

• Contents: Board
• Processor To Be Evaluated: C8051F326/F327
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F326
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F326/7
9.2.
The upper 256 bytes of XRAM functions as USB FIFO space. Figure 9.2 shows an expanded view of the
FIFO space and user XRAM. FIFO space is accessed via USB FIFO registers; see Section “12.5. FIFO
Management” on page 95 for more information on accessing these FIFOs. The FIFO block operates on the
USB clock domain; thus the USB clock must be active when accessing FIFO space.
Important Note: The USB clock must be active when accessing FIFO space.
70
Bits7–3: Unused. Read = 000000b. Write = don’t care.
Bits2–0: PGSEL[1:0]: XRAM Page Select Bits.
User XRAM Space
(System Clock Domain)
R/W
Bit7
-
Accessing USB FIFO Space
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page of
RAM. The upper 6-bits are "don't cares", so the 1k address block is repeated modulo over
the entire 64k external data memory address space.
SFR Definition 9.1. EMI0CN: External Memory Interface Control
R/W
Bit6
-
Figure 9.2. XRAM Memory Map Expanded View
0x03FF
0x0000
R/W
Bit5
-
(1024 bytes)
User XRAM
R/W
Bit4
-
Rev. 1.1
R/W
Bit3
-
0xFF
0xC0
0xBF
0x00
R/W
Bit2
-
OUT (128 bytes)
IN (64 bytes)
Endpoint0
Endpoint1
(64 bytes)
PGSEL1
R/W
Bit1
PGSEL0 00000000
USB FIFO Space
R/W
Bit0
(USB Clock Domain)
SFR Address:
Reset Value
0xAA