C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 187
![BOARD TARGET/PROTO W/C8051F930](/photos/9/25/92560/c8051f930-tb_sml.jpg)
C8051F930-TB
Manufacturer Part Number
C8051F930-TB
Description
BOARD TARGET/PROTO W/C8051F930
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F930-TB
Contents
Board
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F930
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1472
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19. Clocking Sources
C8051F93x-C8051F92x devices include a programmable precision internal oscillator, an external oscillator
drive circuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision
internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as
shown in Figure 19.1. The external oscillator can be configured using the OSCXCN register. The low
power internal oscillator is automatically enabled and disabled when selected and deselected as a clock
source. SmaRTClock operation is described in the SmaRTClock oscillator chapter.
The system clock (SYSCLK) can be derived from the precision internal oscillator, external oscillator, low
power internal oscillator, or SmaRTClock oscillator. The global clock divider can generate a system clock
that is 1, 2, 4, 8, 16, 32, 64, or 128 times slower that the selected input clock source. Oscillator electrical
specifications can be found in the Electrical Specifications Chapter.
The proper way of changing the system clock when both the clock source and the clock divide value are
being changed is as follows:
If switching from a fast “undivided” clock to a slower “undivided” clock:
If switching from a slow “undivided” clock to a faster “undivided” clock:
VDD
Option 2
XTAL2
a. Change the clock divide value.
b. Poll for CLKRDY > 1.
c. Change the clock source.
a. Change the clock source.
b. Change the clock divide value.
c. Poll for CLKRDY > 1.
Option 1
Option 4
10M
XTAL2
Option 3
XTAL2
XTAL1
XTAL2
Figure 19.1. Clocking Sources Block Diagram
OSCICL
Internal Oscillator
Drive Circuit
Oscillator
Precision
External
OSCXCN
EN
OSCICN
Internal Oscillator
Low Power
Rev. 1.1
C8051F93x-C8051F92x
Low Power Internal Oscillator
Precision Internal Oscillator
SmaRTClock
Oscillator
smaRTClock Oscillator
External Oscillator
CLKSEL
Clock Divider
n
CLKRDY
SYSCLK
187
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